2023-06-01 01:13:55 +00:00
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/* processor.v - Connects the different modules comprising the processor
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2023-02-13 16:49:17 +00:00
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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2023-05-11 11:11:17 +00:00
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`include "exec_state_def.v"
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2023-02-11 14:43:53 +00:00
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`include "alu_header.v"
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2023-02-13 15:24:21 +00:00
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`include "config.v"
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2023-11-02 00:29:14 +00:00
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`include "error_header.v"
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2023-05-11 11:11:17 +00:00
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2023-05-11 15:28:10 +00:00
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//HALT: active high
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//IOMEM: 1=IO 0=MEM
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//BHE: active low
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//write: active low
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//read: active low
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//reset: active low
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2023-05-14 15:06:33 +00:00
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module processor (
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2023-06-01 01:13:55 +00:00
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2023-05-14 15:06:33 +00:00
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/* MISC */ input clock, input reset, output wire HALT,output [`ERROR_BITS-1:0] ERROR
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2023-12-03 19:24:12 +00:00
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/* MEMORY / IO */ ,output [19:0] external_address_bus, input [15:0] external_data_bus_read, output [15:0] external_data_bus_write, input wait_state, output read, output write,output BHE,output IOMEM
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2023-06-01 01:13:55 +00:00
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2023-05-14 15:06:33 +00:00
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`ifdef CALCULATE_IPC
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2023-05-27 22:35:00 +00:00
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/* STATISTICS */ ,output wire new_instruction
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2023-05-14 15:06:33 +00:00
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`endif
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2023-11-15 14:37:46 +00:00
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`ifdef OUTPUT_JSON_STATISTICS
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2023-05-21 01:59:53 +00:00
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/* */ ,output wire [`L1_CACHE_SIZE-1:0] L1_SIZE_STAT, output wire VALID_INSTRUCTION_STAT, output wire jump_req_debug
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2023-05-14 15:06:33 +00:00
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`endif
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2023-06-01 01:13:55 +00:00
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);
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2023-05-11 11:11:17 +00:00
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2023-05-27 22:35:00 +00:00
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2023-11-15 14:37:46 +00:00
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`ifdef OUTPUT_JSON_STATISTICS
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2023-05-21 01:59:53 +00:00
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assign jump_req_debug=biu_jump_req;
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`endif
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2023-05-11 11:11:17 +00:00
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/* If there is an error either from the decoder or execution unit set it to ERROR */
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assign ERROR=(DE_ERROR!=`ERR_NO_ERROR)?DE_ERROR:(EXEC_ERROR!=`ERR_NO_ERROR)?EXEC_ERROR:`ERR_NO_ERROR;
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2023-02-14 13:13:40 +00:00
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2023-02-08 12:07:42 +00:00
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2023-05-11 15:28:10 +00:00
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/*############ Execution Unit ################################################### */
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2023-05-11 11:11:17 +00:00
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wire [`ERROR_BITS-1:0] EXEC_ERROR;
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2023-06-01 01:13:55 +00:00
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wire biu_read_request,biu_jump_req,biu_write_request,use_exec_reg_addr;
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2023-05-11 11:11:17 +00:00
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wire [3:0] EXEC_reg_read_port1_addr;
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wire [15:0] ALU_O;
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2023-06-01 01:13:55 +00:00
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wire [7:0] EX2DE_FLAGS;
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wire [15:0] BIU_ADDRESS_INPUT;
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wire reg_write_we;
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wire next_exec;
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2023-05-11 15:28:10 +00:00
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2023-06-01 01:13:55 +00:00
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execute_unit execute_unit (
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/***************** GENERAL *****************/
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/* */ clock, reset, write, EXEC_ERROR
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/*************** INPUT FROM DE ***************/
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/* SYNC SIGNALS */ ,valid_exec_data,set_initial_values
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/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
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/* DATA */ ,PARAM1_INIT,PARAM2_INIT,ProgCount
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/* STATE CONTROL */ ,next_state
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP, ALU_O
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/* OTHER */ ,memio_address_select
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/**************** OUTPUT TO DE ****************/
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/* SYNC SIGNALS */ ,next_exec
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/* FLAGS */ ,EX2DE_FLAGS
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2023-05-27 22:35:00 +00:00
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2023-06-01 01:13:55 +00:00
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/**************** OUTPUT TO BIU ****************/
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/* */ ,BIU_ADDRESS_INPUT
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/* */ ,biu_read_request, biu_jump_req, biu_write_request
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/*************** INPUT FROM BIU ****************/
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2023-11-02 21:48:12 +00:00
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/* */ ,BIU_VALID_DATA,BIU_EX_DATA_READ
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2023-06-01 01:13:55 +00:00
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2023-11-02 21:48:12 +00:00
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/**************** OUTPUT TO BIU ****************/
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/* */ ,BIU_EX_DATA_WRITE
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2023-06-01 01:13:55 +00:00
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/***************** REGISTERS *****************/
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/* */ ,reg_read_port1_data, reg_read_port2_data, EXEC_reg_read_port1_addr
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/* */ ,use_exec_reg_addr, reg_write_we
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);
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2023-05-11 11:11:17 +00:00
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2023-05-07 12:34:15 +00:00
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/*############ Bus Interface Unit ############################################### */
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2023-06-01 01:13:55 +00:00
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wire [15:0] INSTRUCTION_LOCATION;
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wire [15:0] BIU_EX_DATA_READ,BIU_EX_DATA_WRITE;
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wire [31:0] IF2DE_INSTRUCTION;
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wire BIU_VALID_DATA;
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wire VALID_INSTRUCTION;
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BIU BIU(
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/***************** GENERAL *****************/
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/* */ clock,reset
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/**************** OUTSIDE WORLD ****************/
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/* */ ,external_address_bus
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2023-11-02 21:48:12 +00:00
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/* */ ,external_data_bus_read,external_data_bus_write,read,write,BHE,IOMEM
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2023-12-03 19:24:12 +00:00
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/* */ ,wait_state
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/**************** OUTPUT TO DE ****************/
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/* */ ,IF2DE_INSTRUCTION,VALID_INSTRUCTION,INSTRUCTION_LOCATION
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/* */ ,BIU_VALID_DATA
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/**************** INPUT FROM DE ****************/
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,Wbit,MEM_OR_IO,VALID_INSTRUCTION_ACK
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/**************** INPUT FROM EX ****************/
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/* */ ,biu_jump_req,biu_write_request,biu_read_request
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2023-11-02 21:48:12 +00:00
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/* */ ,BIU_ADDRESS_INPUT,BIU_EX_DATA_WRITE
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2023-11-02 21:48:12 +00:00
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/***************** OUTPUT TO EX ****************/
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/* */ ,BIU_EX_DATA_READ
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2023-06-01 01:13:55 +00:00
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2023-11-15 14:37:46 +00:00
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`ifdef OUTPUT_JSON_STATISTICS
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2023-06-01 01:13:55 +00:00
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/***************** STATISTICS *****************/
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/* */ ,L1_SIZE_STAT, VALID_INSTRUCTION_STAT
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2023-05-14 15:06:33 +00:00
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`endif
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2023-05-13 05:51:35 +00:00
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2023-06-01 01:13:55 +00:00
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);
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2023-05-07 12:34:15 +00:00
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2023-02-22 01:28:23 +00:00
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/*############ Decoder ########################################################## */
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2023-05-11 15:28:10 +00:00
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2023-06-01 01:13:55 +00:00
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wire [`ERROR_BITS-1:0] DE_ERROR;
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wire valid_exec_data, set_initial_values, Wbit;
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wire memio_address_select, MEM_OR_IO, VALID_INSTRUCTION_ACK;
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wire [1:0] in_alu_sel1, in_alu_sel2;
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wire [2:0] IN_MOD,OUT_MOD, RM;
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wire [3:0] DE_reg_read_port1_addr,DE_reg_read_port2_addr, reg_write_addr;
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wire [15:0] PARAM1_INIT, PARAM2_INIT, ProgCount;
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wire [`ALU_OP_BITS-1:0] ALU_OP;
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wire [`EXEC_STATE_BITS-1:0] next_state;
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2023-05-13 12:45:15 +00:00
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2023-02-17 18:08:09 +00:00
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decoder decoder(
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/***************** GENERAL *****************/
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/* Input from sys. */ clock, reset
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/* Output to sys. */ ,MEM_OR_IO, DE_ERROR, HALT
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2023-02-22 01:28:23 +00:00
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2023-06-01 01:13:55 +00:00
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/*************** INPUT FROM IF ***************/
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/* */ ,IF2DE_INSTRUCTION, VALID_INSTRUCTION
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/* */ ,INSTRUCTION_LOCATION
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2023-06-01 01:13:55 +00:00
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/*************** OUTPUT TO IF ***************/
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/* */ ,VALID_INSTRUCTION_ACK
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2023-06-01 01:13:55 +00:00
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/*************** INPUT FROM EX ***************/
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/* */ ,EX2DE_FLAGS[7:0], next_exec
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2023-05-11 15:28:10 +00:00
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2023-06-01 01:13:55 +00:00
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/*************** OUTPUT TO DE ***************/
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/* SYNC SIGNALS */ ,set_initial_values, valid_exec_data
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/* INSTR. PARAMS */ ,Wbit, IN_MOD, OUT_MOD, RM
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/* DATA */ ,PARAM1_INIT, PARAM2_INIT, ProgCount
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/* STATE CONTROL */ ,next_state
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/* ALU CONTROL */ ,in_alu_sel1, in_alu_sel2, ALU_OP
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/* OTHER */ ,memio_address_select
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2023-05-11 15:28:10 +00:00
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2023-06-01 01:13:55 +00:00
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/************* OUTPUT TO REGISTERS ************/
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/* */ , reg_write_addr,DE_reg_read_port2_addr, DE_reg_read_port1_addr
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2023-02-22 01:28:23 +00:00
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2023-06-01 01:13:55 +00:00
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`ifdef CALCULATE_IPC
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/* STATISTICS */ , new_instruction
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`endif
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2023-05-11 15:28:10 +00:00
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2023-06-01 01:13:55 +00:00
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);
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/*############ Registers ######################################################## */
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2023-02-17 18:08:09 +00:00
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2023-02-12 01:05:39 +00:00
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2023-05-11 11:11:17 +00:00
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wire [3:0] reg_read_port1_addr;
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2023-05-11 15:28:10 +00:00
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assign reg_read_port1_addr = use_exec_reg_addr ? EXEC_reg_read_port1_addr : DE_reg_read_port1_addr;
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2023-05-11 11:11:17 +00:00
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2023-05-11 15:28:10 +00:00
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wire [15:0] reg_read_port1_data, reg_read_port2_data;
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2023-03-03 06:29:06 +00:00
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2023-05-11 15:28:10 +00:00
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register_file register_file(
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2023-11-25 04:11:51 +00:00
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/* WRITE */ .write_port1_addr(reg_write_addr), //TODO: should this come from exec instead?
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2023-05-11 15:28:10 +00:00
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/* */ .write_port1_data(ALU_O),
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/* */ .write_port1_we(reg_write_we),
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/* READ 1 */ .read_port1_addr(reg_read_port1_addr),
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/* */ .read_port1_data(reg_read_port1_data),
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/* READ 2 */ .read_port2_addr(DE_reg_read_port2_addr),
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2023-11-15 18:43:03 +00:00
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/* */ .read_port2_data(reg_read_port2_data),
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/* GENERAL */ .clock(clock)
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);
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2023-02-10 01:45:27 +00:00
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2023-05-27 22:35:00 +00:00
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/*############################################################################### */
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2023-05-13 05:51:35 +00:00
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2023-02-08 09:18:00 +00:00
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endmodule
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