fde181aa66
Project: Fixed verilator warnings for fpga_sim
2024-02-26 13:12:26 +00:00
aac55f7038
I2C_BOOTLOADER: Added support for error handling
2024-02-10 22:35:33 +00:00
be402aa8f7
Project: updated copyright notices and README and fixed a few spelling mistakes
2024-02-10 15:52:13 +00:00
1966ab78b4
Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
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I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
1d9be44c5a
Build system: renamed upload to upload_bitstream to allow for an upload_firmware in the future
2024-01-22 20:19:14 +00:00
8281c9a21f
FPGA_Board/OrangeCrab_r0.2.1: Switched the GPIO 0/1 pins for I2C to the dedicated ones
2023-12-10 04:37:07 +00:00
65dfd21ef0
Peripherals/I2C_driver: Uncommented code to check for device acknowledgment
2023-12-09 00:53:52 +00:00
533f346f9b
Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
2023-12-07 16:39:04 +00:00
b1108e375d
Build system: Fixed standalone ./system/Makefile build and general Makefile improvements
2023-12-06 18:13:24 +00:00
8edafd70cf
Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies
2023-12-05 21:46:56 +00:00
2fcc521f12
Peripherals/Wishbone_memory: Rewrote the module to be more efficient, smaller and also support byte level addressing. It is correct enough now to run code out of!
2023-12-05 02:50:21 +00:00
26210be950
Peripherals/I2C_driver: Corrected the implementation of the bidirectional SDA pin, fixing the final yosys 0.35 warning
2023-12-04 22:40:53 +00:00
63ea29e399
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
2023-12-03 19:24:39 +00:00
aedefddb5d
Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
2023-11-15 18:43:56 +00:00
29bc2e6d96
Project: Cleaned up some code and run the project through aspell
2023-11-15 14:37:46 +00:00
09ccce5f30
Peripherals/HD44780: Rewrote and cleaned up a lot of the driver code. Unfortunately what i think is a very weird bug in yosys is still affecting the codebase
2023-11-15 00:26:46 +00:00
2c8e8a9d9c
Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
2023-11-12 21:39:27 +00:00
7d2cb5672f
Reduced numbers to be sorted in gnome_sort.asm to fit in lcd, fixed hlt on real hardware, slowed down cpu, increased lcd fifo and with that I almost got gnome_sort.asm working perfectly on real hardware
2023-11-12 07:31:05 +00:00
a88c420ca5
Added an I2C driver, a PCF8574 driver and an HD44780 display driver. Unfortunately this shows that even fibonacci doesn't run correctly. Nonetheless, I made colored_led.asm output text to the display!
2023-11-09 22:10:55 +00:00
1a1634c673
Updated README, improved fpga-specific makefile options and updated the version number
2023-11-07 14:37:22 +00:00
01dcbfa7a1
The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
2023-11-06 08:13:36 +00:00
934e2f5a36
Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
2023-11-02 23:46:12 +00:00
601397b7f0
Properly added fpga_top.v stuff in the build system and fixed some syntax errors
2023-11-02 22:00:07 +00:00
36bf8f9c7a
Added OrangeCrab board-specific code to connect the cpu to the outside world
2023-11-02 20:40:04 +00:00
5feee9de57
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
