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be402aa8f7
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Project: updated copyright notices and README and fixed a few spelling mistakes
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2024-02-10 15:52:13 +00:00 |
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aedefddb5d
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Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
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2023-11-15 18:43:56 +00:00 |
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fa62b07c14
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Removed probably unnecessary high impedance case yosys was complaining about in registers.v
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2023-11-12 03:13:22 +00:00 |
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b7bfbd4e33
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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bd7610879f
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Removed erroneous file and run aspell
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2023-03-21 14:51:39 +00:00 |
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82baacfd5b
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Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints
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2023-03-12 08:55:40 +00:00 |
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9230900b75
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fixed verilator lint warnings relating code enabled with debug options from config.v
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2023-03-12 08:12:01 +00:00 |
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ba52ff89e6
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Fixed most problems verilator's linter found
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2023-03-04 06:22:28 +00:00 |
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abee49d6c3
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Implemented PUSH instruction, fixed register addressing bug and a RET bug
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2023-02-24 07:32:27 +00:00 |
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7fde422341
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Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
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2023-02-22 01:28:23 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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