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6b9d0c49fb
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Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:23:35 +00:00 |
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3ec90b1843
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Added version stamp and last commit to json log
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2023-11-01 06:03:53 +00:00 |
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3a63e916f5
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Added cycles to waveform capture for icarus verilog
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2023-10-31 19:32:35 +00:00 |
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49335a2c2f
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Fixed a small bug in log generation and did some cleanup
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2023-10-31 19:01:34 +00:00 |
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8a62b89a13
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Fixed small bug with json data reporting and improved slightly the graphs
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2023-10-30 08:01:03 +00:00 |
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42c319d55d
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Lots of cleanup mainly on processor.v
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2023-06-01 02:13:55 +01:00 |
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0bf00df07c
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Fixed clock cycle and instruction counter overflow
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2023-05-23 09:27:46 +01:00 |
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e74d73ed58
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Added reporting of branches on the stat json files and improved the plotting script
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2023-05-21 03:00:27 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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f4b22951d0
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Cleaned up some pieces of code and fixed a bug
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2023-05-04 00:49:04 +01:00 |
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aabe62b4c9
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Added missing copyright and license notice
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2023-03-09 06:13:34 +00:00 |
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11624ca2d2
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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9de83fd7c1
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Added partial support for the software interrupt INT instruction
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2023-03-08 07:26:28 +00:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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