18 lines
605 B
Verilog
18 lines
605 B
Verilog
`define CPU_SPEED 1000
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module system ( input clock,input reset, output [19:0]address_bus, inout [15:0]data_bus,output BHE, output rd, output wr, output IOMEM, output HALT, output ERROR);
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processor p(clock,reset,address_bus,data_bus,rd,wr,BHE,IOMEM,HALT,ERROR);
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doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM);
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string memdump_name;
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always @(posedge HALT) begin
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// $display("Processor halted.\nCycles run for: %d",cycles);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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// #(`CPU_SPEED) //Just for the waveform
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$finish;
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end
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endmodule
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