57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
`timescale 1ns/1ps
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module system ( input clock,input reset, output [19:0]address_bus, inout [15:0]data_bus,output BHE, output rd, output wr, output IOMEM, output HALT, output ERROR);
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processor p(clock,reset,address_bus,data_bus,rd,wr,BHE,IOMEM,HALT,ERROR);
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doublemem sysmem(address_bus,data_bus,rd,wr,BHE,IOMEM);
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string waveform_name;
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initial begin
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p);
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end
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end
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reg [1:0] finish;
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string memdump_name;
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always @(posedge HALT) begin
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$display("Processor halted.\nCycles run for: %d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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always @(posedge clock) begin
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/* Allow some clock cycles for the waveform*/
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case(finish)
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2'd0: begin end
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2'd1: finish <= 2;
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2'd2: finish <= 3;
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2'd3: $finish;
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endcase
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end
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always @(posedge ERROR) begin
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$display("PROCESSOR RUN INTO AN ERROR.\nCycles run for: %d",cycles-1);
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if($value$plusargs("MEMDUMP=%s",memdump_name))begin
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$writememh(memdump_name, system.sysmem.memory,0,32767);
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end
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finish<=2'd1;
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end
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integer cycles=0;
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always @(posedge clock)begin
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if(reset==1)
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cycles<=cycles+1;
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else
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cycles<=0;
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end
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endmodule
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