1966ab78b4
Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
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I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
3e66336456
Build system: Small fixes and corrected rebuild when only the verilator testbench was changed
2023-12-09 02:39:14 +00:00
94bc6eba39
Build system: Added help text and target mrproper which also deletes downloaded source code
2023-12-08 22:10:11 +00:00
bc1dcacfc0
Build system: Fixed a bug with building the boot_code/ directory with a lot of make jobs
2023-12-07 18:45:29 +00:00
48249e8051
Forgot to add some of the files for the previous commit
2023-12-06 18:38:32 +00:00
c1e597feba
Build system: added handling for building on systems without git
2023-12-06 00:23:24 +00:00
8edafd70cf
Build system: Improved the handling of seeds, moved most of the board specific build instructions to the board specific .mk file and fixed bios.asm dependencies
2023-12-05 21:46:56 +00:00
63ea29e399
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
2023-12-03 19:24:39 +00:00
1a1634c673
Updated README, improved fpga-specific makefile options and updated the version number
2023-11-07 14:37:22 +00:00
5feee9de57
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
b2972c9938
release v0.2.0 - Pipelined milestone
2023-11-01 06:08:12 +00:00
3ec90b1843
Added version stamp and last commit to json log
2023-11-01 06:03:53 +00:00
07d2a80b2e
Added code to record statistics and a tool to plot them
2023-05-14 16:06:33 +01:00
9de83fd7c1
Added partial support for the software interrupt INT instruction
2023-03-08 07:26:28 +00:00
8070d4e58a
Improved build system's handling of verilator
2023-03-05 23:11:18 +00:00
99cbc49e95
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
5705b8e8a5
Added support for Verilator!
2023-03-04 08:37:43 +00:00
6e8d951360
Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
2023-02-24 17:38:23 +00:00
cac01f0333
Fixed Makefile bug
2023-02-22 01:51:14 +00:00
e2e9a92832
Cleaned the decoder a bit and laid down some of the groundwork for microcode
2023-02-19 16:22:23 +00:00
82bd859874
Moved the decoding of opcodes into a separate module and optimised memory reads
2023-02-17 18:08:09 +00:00
ed3d7101d3
Further improved build system and changed brainfuck print message
2023-02-16 23:26:32 +00:00
ded47555a5
Improved build system and project directory structure
2023-02-16 01:52:02 +00:00
