(Tim) Efthimis Kritikos Efthimis
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Efthimis pushed to master at Efthimis/9086 2023-02-09 14:55:22 +00:00
be31d74f74 Fixed warning about standards compliance
a166efec9c Moved clock generator to the testbench
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Efthimis pushed to master at Efthimis/9086 2023-02-09 14:46:21 +00:00
c3a2f5eb01 Added primitive decode stage, improved state handling and fixed CIR register
76572a39ad Fix documentation
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Efthimis pushed to master at Efthimis/9086 2023-02-08 23:59:01 +00:00
5371caa3bb Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
08bf5d3031 Cleaned up and added opcode examples in the 8086 doc
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Efthimis pushed to master at Efthimis/9086 2023-02-08 20:55:53 +00:00
eefea44673 Removed erroneous backup file
Efthimis pushed to master at Efthimis/9086 2023-02-08 20:53:35 +00:00
361d98b7e6 Added some documentation for the 8086 opcodes
Efthimis pushed to master at Efthimis/Testing 2023-02-08 13:03:18 +00:00
5a991d4886 Testing markdown rendering
Efthimis pushed to master at Efthimis/9086 2023-02-08 12:38:38 +00:00
139ec3c0c0 Standardised indentation
61a403271c Added ROM, address and data buses and primitive program counter
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Efthimis pushed to master at Efthimis/9086 2023-02-08 09:36:29 +00:00
bc2ef977d8 Improved state logic
f9393cb69f Basic start for the control block
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Efthimis created repository Efthimis/9086 2023-02-08 08:38:10 +00:00
Efthimis pushed to master at Efthimis/COMS30046_2022_TB-2_playground 2023-02-07 17:58:00 +00:00
aeba97df05 Didn't add all files on last commit
Efthimis pushed to master at Efthimis/COMS30046_2022_TB-2_playground 2023-02-07 17:56:20 +00:00
a13ffe57b6 Fixed VPP typo. should be VVP
d8f6c595a2 Added clock and gtkwave integration
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Efthimis pushed to master at Efthimis/COMS30046_2022_TB-2_playground 2023-02-06 21:09:52 +00:00
b749a5610e Fixed git ignore and cleanup
Efthimis created branch master in Efthimis/COMS30046_2022_TB-2_playground 2023-02-06 15:46:41 +00:00
Efthimis pushed to master at Efthimis/COMS30046_2022_TB-2_playground 2023-02-06 15:46:41 +00:00
a0c2413b85 First try at the Verilog VPI
9b350ec117 Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore
fb8208ef55 Dipping my toes into verilog development
Efthimis created repository Efthimis/COMS30046_2022_TB-2_playground 2023-02-06 15:45:34 +00:00
Efthimis created branch master in Efthimis/Testing 2023-02-04 21:59:51 +00:00
Efthimis pushed to master at Efthimis/Testing 2023-02-04 21:59:51 +00:00
8291b83486 first commit
Efthimis created repository Efthimis/Testing 2023-02-04 21:29:46 +00:00