Efthimis/COMS30046_2022_TB-2_playground
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Testing out mostly HDL and specifically verilog stuff
6 Commits 1 Branch 0 Tags 49 KiB
Verilog 52%
Coq 20.6%
C 14.9%
Makefile 12.5%
a13ffe57b6
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(Tim) Efthymios Kritikos a13ffe57b6 Fixed VPP typo. should be VVP
2023-02-07 17:55:57 +00:00
verilog_iverilog Fixed VPP typo. should be VVP 2023-02-07 17:55:57 +00:00
.gitignore Added clock and gtkwave integration 2023-02-07 17:52:02 +00:00