Testing out mostly HDL and specifically verilog stuff

(Tim) Efthymios Kritikos 9b350ec117 Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore		2023-01-24 20:27:15 +00:00
verilog_iverilog	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00
.gitignore	Wrote my first verilog project ( a multiplexer ) with a testbench and added a .gitignore	2023-01-24 20:27:15 +00:00