From 9b350ec1177b166f5c35e058fe38d23959350894 Mon Sep 17 00:00:00 2001
From: "(Tim) Efthymios Kritikos" <efkf@firemail.cc>
Date: Tue, 24 Jan 2023 20:27:15 +0000
Subject: [PATCH] Wrote my first verilog project ( a multiplexer ) with a
 testbench and added a .gitignore

---
 .gitignore                                    |  1 +
 verilog_iverilog/multiplexer/Makefile         | 11 ++++
 verilog_iverilog/multiplexer/multiplexer-tb.v | 50 +++++++++++++++++++
 verilog_iverilog/multiplexer/multiplexer.v    |  8 +++
 4 files changed, 70 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 verilog_iverilog/multiplexer/Makefile
 create mode 100644 verilog_iverilog/multiplexer/multiplexer-tb.v
 create mode 100644 verilog_iverilog/multiplexer/multiplexer.v

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..6b3bb45
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*.vpp
diff --git a/verilog_iverilog/multiplexer/Makefile b/verilog_iverilog/multiplexer/Makefile
new file mode 100644
index 0000000..f79db3e
--- /dev/null
+++ b/verilog_iverilog/multiplexer/Makefile
@@ -0,0 +1,11 @@
+SOURCES=multiplexer.v multiplexer-tb.v
+VPP=multiplexer.vpp
+
+run: ${VPP}
+	vvp ${VPP}
+
+${VPP} : ${SOURCES}
+	iverilog $^ -o $@
+
+clean:
+	rm -f ${VPP}
diff --git a/verilog_iverilog/multiplexer/multiplexer-tb.v b/verilog_iverilog/multiplexer/multiplexer-tb.v
new file mode 100644
index 0000000..bf2ac90
--- /dev/null
+++ b/verilog_iverilog/multiplexer/multiplexer-tb.v
@@ -0,0 +1,50 @@
+module hello;
+	wire out;
+	reg A,B,X;
+	multiplexer idk(A,B,X,out);
+initial 
+begin
+	$display("RSLT\tOUT\tA\tB\tSLCT");
+	A=1;B=1;X=1;#50
+	if(out==1)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=1;B=0;X=1;#50
+	if(out==0)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=0;B=1;X=1;#50
+	if(out==1)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=0;B=0;X=1;#50
+	if(out==0)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=1;B=1;X=0;#50
+	if(out==1)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=1;B=0;X=0;#50
+	if(out==1)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=0;B=1;X=0;#50
+	if(out==0)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	A=0;B=0;X=0;#50
+	if(out==0)
+		$display("PASS\t%b\t%b\t%b\t%b",out,A,B,X);
+	else
+		$display("FAIL\t%b\t%b\t%b\t%b",out,A,B,X);
+	$finish ;
+end
+endmodule
diff --git a/verilog_iverilog/multiplexer/multiplexer.v b/verilog_iverilog/multiplexer/multiplexer.v
new file mode 100644
index 0000000..6e372c9
--- /dev/null
+++ b/verilog_iverilog/multiplexer/multiplexer.v
@@ -0,0 +1,8 @@
+module multiplexer(A,B,X,out1);
+input A,B,X;
+output out1;
+
+assign out1 = (~X&A)|(B&X);
+
+endmodule
+