9086/system
(Tim) Efthimis Kritikos 1966ab78b4 Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
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external_ip Added .keep file for intentionally empty directory 2023-12-03 19:30:59 +00:00
fpga_config/OrangeCrab_r0.2.1 Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom 2024-02-09 23:30:58 +00:00
peripherals Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom 2024-02-09 23:30:58 +00:00
alu_header.v Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00
alu.v More small fixes 2023-11-04 08:31:05 +00:00
biu.v Project: Removed some unused verilator warning restrictions and a TODO comment 2023-12-06 02:46:39 +00:00
boot_code.asm Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
config.v Peripherals/BuiltinRam: Fixed high impedance warning in yosys 2023-12-04 17:04:22 +00:00
decoder.v Project: Removed some unused verilator warning restrictions and a TODO comment 2023-12-06 02:46:39 +00:00
error_header.v First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching 2023-05-07 13:34:15 +01:00
exec_state_def.v Removed more "conflicting driver" issues with yet more performance penalties... 2023-11-04 15:33:23 +00:00
execute.v Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space 2023-11-25 04:12:05 +00:00
general.v Cleaned up some pieces of code and fixed a bug 2023-05-04 00:49:04 +01:00
Makefile Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom 2024-02-09 23:30:58 +00:00
memory.v Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom 2024-02-09 23:30:58 +00:00
processor.v Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
registers.v Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!! 2023-11-15 18:43:56 +00:00
system.v Project: Removed some unused verilator warning restrictions and a TODO comment 2023-12-06 02:46:39 +00:00
testbench.cpp Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation 2023-11-04 11:04:22 +00:00
testbench.v Processor/Instructions: Added support for the IN <immediate> instruction. Also changed some stuff in system.v to add more devices in the IO/Memory space 2023-11-25 04:12:05 +00:00
ucode_header.v Added partial support for the software interrupt INT instruction 2023-03-08 07:26:28 +00:00
ucode.txt Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
verilator_makefile Removed erroneous file and run aspell 2023-03-21 14:51:39 +00:00
verilator_makefile_fpga Build system: Small fixes and corrected rebuild when only the verilator testbench was changed 2023-12-09 02:39:14 +00:00