Peripherals/I2C_driver: Corrected the implementation of the bidirectional SDA pin, fixing the final yosys 0.35 warning

README.md

@@ -48,16 +48,13 @@ Additionally, for ECP5 FPGAs:
 * prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
 * nextpnr : 0.6
 
-Additionally, if you need a DRAM/DDR controller, the project supports litedram:
-
-* Litedram : 2023.08
-* Migen : 0.9.2
-* Litex : 2023.08
-
 Additionally, for FPGAs using the [foboot](https://github.com/im-tomu/foboot) bootloader
 
 * dfu-util : 0.11
 
+Additionally, if you need a DRAM/DDR controller, the project supports litedram but all the dependencies
+needed to build it are downloaded automatically by the appropriate script.
+
 ### High level design overview
 
 <img width="700" style=" margin: 10px 0px 10px 10px;" alt="9086 logo" src="readme_files/9086_overview.svg">

system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v

@@ -411,14 +411,15 @@ pcf8574_for_HD44780 PCF8574_driver(
 
 // I2C driver
 
-wire SCL,SDA,I2C_BUSY,I2C_SEND;
+wire SCL,SDA_input,SDA_output,SDA_direction,I2C_BUSY,I2C_SEND;
 assign gpio_1=SCL;
-assign gpio_0=SDA;
 
 I2C_driver i2c_driver(
 	.clock(I2C_SPEED),
 
-	.SDA_(SDA),
+	.SDA_input(SDA_input),
+	.SDA_output(SDA_output),
+	.SDA_direction(SDA_direction),
 	.SCL(SCL),
 
 	.address(7'h27),
@@ -427,4 +428,19 @@ I2C_driver i2c_driver(
 	.i2c_data(i2c_data)
 );
 
+TRELLIS_IO #(
+	// Parameters.
+	.DIR ("BIDIR")
+) TRELLIS_IO_00 (
+	// pin
+	.B (gpio_0),
+	//input
+	.I (1'd0),
+	//Direction
+	.T (~( SDA_direction & (~SDA_output) )),
+	// Output
+	.O (SDA_input)
+);
+
+
 endmodule

system/peripherals/I2C_driver.v

@@ -19,7 +19,9 @@
 
 module I2C_driver (
 	input wire clock,
-	inout wire SDA_,
+	input wire SDA_input,
+	output wire SDA_output,
+	output reg SDA_direction, //1:output 0:input
 	output reg SCL,
 
 	input wire [6:0] address,
@@ -30,8 +32,7 @@ module I2C_driver (
 
 reg SDA;
 
-reg i2c_bus_dir=0;
+assign SDA_output=SDA;
-assign SDA_=(i2c_bus_dir==0)?SDA:1'bz;
 
 reg [5:0] i2c_state = 6'b100100;
 
@@ -43,7 +44,7 @@ always @(posedge clock) begin
 	case (i2c_state)
 	/***** start sequence ******/
 		6'b000000:begin
-			i2c_bus_dir<=0;
+			SDA_direction<=1;
 			SDA<=1;
 			SCL<=1;
 			i2c_state<=6'b000001;
@@ -103,7 +104,7 @@ always @(posedge clock) begin
 	/****** Acknowledge ********/
 		6'b001011:begin
 			SCL<=0;
-			i2c_bus_dir<=1;
+			SDA_direction<=0;
 			i2c_state<=6'b001100;
 		end
 		6'b001100:begin
@@ -152,7 +153,7 @@ always @(posedge clock) begin
 	/****** Send data ********/
 		6'b010100:begin
 			SCL<=0;
-			i2c_bus_dir<=0;
+			SDA_direction<=1;
 			i2c_state<=6'b010101;
 		end
 		6'b010101:begin
@@ -175,7 +176,7 @@ always @(posedge clock) begin
 		end
 	/****** Acknowledge ********/
 		6'b011000:begin
-			i2c_bus_dir<=1;
+			SDA_direction<=0;
 			SCL<=0;
 			i2c_state<=6'b011001;
 		end
@@ -194,7 +195,7 @@ always @(posedge clock) begin
 		//		i2c_state<=6'b011111;
 		//	end else begin
 				i2c_state<=6'b011100;
-				i2c_bus_dir<=0;
+				SDA_direction<=1;
 		//	end
 		end
 	/****** separator ********/