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A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.
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(Tim) Efthimis Kritikos 26210be950 Peripherals/I2C_driver: Corrected the implementation of the bidirectional SDA pin, fixing the final yosys 0.35 warning
2023-12-04 22:40:53 +00:00
boot_code Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
readme_files Made the temporary logo a bit more centered. Also removed an incorrect line in README 2023-10-24 01:08:13 +01:00
system Peripherals/I2C_driver: Corrected the implementation of the bidirectional SDA pin, fixing the final yosys 0.35 warning 2023-12-04 22:40:53 +00:00
tools Tools/Gen_litedram: Major improvements and cleanup including work in ensuring it is reproducible 2023-12-04 21:36:48 +00:00
.gitignore Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
8086_documentation.md Changed slogan and cleaned up some small pieces of code 2023-05-23 16:18:33 +01:00
common.mk Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
COPYING Properly licensed the project and run it through aspell 2023-02-13 16:49:17 +00:00
gtkwave_savefile.gtkw Lots of cleanup mainly on processor.v 2023-06-01 02:13:55 +01:00
Makefile Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
README.md Documentation: Updated README.md with the improvements in gen_litedram.sh 2023-12-04 22:32:21 +00:00

README.md

9086 logo

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

  • 8086
    • Executing code
    • Is Turing complete
    • Can boot up MS-DOS / FreeDOS
    • Is completely binary compatible
    • Is pipelined
    • Is Out of Order
    • Is superscalar
    • Has been successfully synthesized
    • Has a comprehensive testing framework

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on ./common.mk. This list shows the software needed and the versions used during development :

  • Icarus Verilog : version 12.0 OR (preferred) Verilator : 5.016
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.4

After that you can run make on the top level directory and it should build everything and start the simulation

Synthesis and bitstream creation for FPGAs

You need to set FPGA_BOARD in ./common.mk to the name of a directory inside ./system/fpga_config/. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run make upload in the top level directory and it should create the bitstream and upload it.

These are the currently supported FPGA boards:

  • OrangeCrab r0.2.1

This list shows the software needed and the versions used during development :

  • yosys : 0.35
  • bin86 : 0.16.21
  • GNU Make : 4.4.1
  • xxd : 2022-01-14
  • POSIX coreutils : GNU coreutils 9.4

Additionally, for ECP5 FPGAs:

  • prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
  • nextpnr : 0.6

Additionally, for FPGAs using the foboot bootloader

  • dfu-util : 0.11

Additionally, if you need a DRAM/DDR controller, the project supports litedram but all the dependencies needed to build it are downloaded automatically by the appropriate script.

High level design overview

9086 logo

License and Copyright

All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

File Copyright owner Original license
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf Greg Davill MIT

Version names

The version name consist of three numbers:

  1. The CPU that this version aims to be compatible with
  2. The specific milestone
  3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached. A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.