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1b510e4781
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Made the size of the cache variable
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2023-05-18 11:21:27 +01:00 |
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53e9d371d7
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Fully optimised BIU. Now it can instantly deliver instructions back to back
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2023-05-16 18:07:28 +01:00 |
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bfa576e2a0
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Cleaned up the interface between BIU and the processor
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2023-05-16 13:33:08 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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00aa828ddc
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Improved parallelism
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2023-05-13 10:52:44 +01:00 |
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fe0426a77b
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Made execute unit run in parallel with everything else. Still not parallel for most of the time though
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2023-05-13 06:51:35 +01:00 |
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7151d5634f
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Fixed bug that prevented Icarus Verilog from simulating correctly
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2023-05-11 19:55:47 +01:00 |
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539fb8416b
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Fixed copyright notices, did some major cleanup and bumped README's versions
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2023-05-11 16:28:10 +01:00 |
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7724e5f383
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Removed deprecated BIU_NEXT_POSITION
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2023-05-10 08:53:29 +01:00 |
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7e612bb701
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made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
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2023-05-10 08:31:14 +01:00 |
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c854818d6d
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Tightened up write timing
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2023-05-10 04:43:09 +01:00 |
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b7bfbd4e33
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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