|
|
c3a2f5eb01
|
Added primitive decode stage, improved state handling and fixed CIR register
|
2023-02-09 14:46:21 +00:00 |
|
|
|
5371caa3bb
|
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
|
2023-02-08 23:59:06 +00:00 |
|
|
|
139ec3c0c0
|
Standardised indentation
|
2023-02-08 12:09:21 +00:00 |
|
|
|
61a403271c
|
Added ROM, address and data buses and primitive program counter
|
2023-02-08 11:57:22 +00:00 |
|
|
|
f9393cb69f
|
Basic start for the control block
|
2023-02-08 09:18:00 +00:00 |
|
