24 lines
333 B
Verilog
24 lines
333 B
Verilog
module tb;
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wire clock;
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reg reset;
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reg clk_enable;
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processor p(clock,reset);
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clock_gen #(.FREQ(1000)) u1(clk_enable, clock);
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initial begin
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$dumpfile("test.lx2");
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$dumpvars(0,p);
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clk_enable <= 1;
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#($random%500)
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reset = 0;
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#(100)
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reset = 1;
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#(10000)
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#50 $finish;
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end
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endmodule
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