Commit Graph

12 Commits

Author SHA1 Message Date
8c921380bc Peripherals/BuiltinRam: Fixed high impedance warning in yosys 2023-12-04 17:04:22 +00:00
63ea29e399 Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
29bc2e6d96 Project: Cleaned up some code and run the project through aspell 2023-11-15 14:37:46 +00:00
01dcbfa7a1 The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality 2023-11-06 08:13:36 +00:00
df2975fa09 Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation 2023-11-04 11:04:22 +00:00
08aac5c7b6 Removed some code that wasn't meant for synthesis and fixed important bug in Makefile 2023-11-02 22:19:15 +00:00
1b510e4781 Made the size of the cache variable 2023-05-18 11:21:27 +01:00
53e9d371d7 Fully optimised BIU. Now it can instantly deliver instructions back to back 2023-05-16 18:07:28 +01:00
07d2a80b2e Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
539fb8416b Fixed copyright notices, did some major cleanup and bumped README's versions 2023-05-11 16:28:10 +01:00
b7bfbd4e33 Improved BIU performance and debug messages 2023-05-10 04:05:56 +01:00
ded47555a5 Improved build system and project directory structure 2023-02-16 01:52:02 +00:00