Commit Graph

17 Commits

Author SHA1 Message Date
63ea29e399 Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU) 2023-12-03 19:24:39 +00:00
98d30a1813 Project: removed a .fst.hier file thought to be generated by gtkwave and added the type to gitignore 2023-11-15 00:32:40 +00:00
e06c0eeaa0 Made the build system simplify the microcode so that yosys understands and synthesises it! Now gnome_sort.asm almost works! 2023-11-12 04:04:56 +00:00
5feee9de57 Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA 2023-11-02 00:29:14 +00:00
021dd06e9a Added support for some more instructions, fixed a bug in CMP and also added a program that uses them 2023-05-19 17:59:20 +01:00
07d2a80b2e Added code to record statistics and a tool to plot them 2023-05-14 16:06:33 +01:00
99cbc49e95 Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation 2023-03-05 00:10:55 +00:00
5705b8e8a5 Added support for Verilator! 2023-03-04 08:37:43 +00:00
b00cd988cf Cleaned up boot_code 2023-03-03 19:36:28 +00:00
619702384b Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set 2023-02-19 21:42:59 +00:00
ded47555a5 Improved build system and project directory structure 2023-02-16 01:52:02 +00:00
037f6dd7da Added support for writing to memory 2023-02-14 13:13:40 +00:00
d7eb4f36c0 Wrote very basic brainfuck interpreter in 8086 asm to work on making it run and prove Turing completeness 2023-02-11 01:12:54 +00:00
fc4ecdb8d2 Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing 2023-02-10 18:21:19 +00:00
19fcf11f63 Still hadn't added all files from the assembler commit. Also fixed .gitignore 2023-02-10 13:32:51 +00:00
5371caa3bb Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc 2023-02-08 23:59:06 +00:00
f9393cb69f Basic start for the control block 2023-02-08 09:18:00 +00:00