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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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8070d4e58a
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Improved build system's handling of verilator
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2023-03-05 23:11:18 +00:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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cac01f0333
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Fixed Makefile bug
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2023-02-22 01:51:14 +00:00 |
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7fde422341
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Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
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2023-02-22 01:28:23 +00:00 |
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e2e9a92832
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Cleaned the decoder a bit and laid down some of the groundwork for microcode
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2023-02-19 16:22:23 +00:00 |
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fd4a9b5442
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Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
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2023-02-19 00:20:53 +00:00 |
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82bd859874
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Moved the decoding of opcodes into a separate module and optimised memory reads
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2023-02-17 18:08:09 +00:00 |
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ed3d7101d3
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Further improved build system and changed brainfuck print message
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2023-02-16 23:26:32 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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