|
|
6b9d0c49fb
|
Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
|
2023-11-02 00:23:35 +00:00 |
|
|
|
85512d5ace
|
Last minute fix of dependencies in Makefile before release
|
2023-11-01 19:09:59 +00:00 |
|
|
|
07d2a80b2e
|
Added code to record statistics and a tool to plot them
|
2023-05-14 16:06:33 +01:00 |
|
|
|
a8ab6b2dc7
|
Separated the execution unit from decode
|
2023-05-11 12:22:49 +01:00 |
|
|
|
da51dd6da7
|
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
|
2023-05-07 13:34:15 +01:00 |
|
|
|
8070d4e58a
|
Improved build system's handling of verilator
|
2023-03-05 23:11:18 +00:00 |
|
|
|
99cbc49e95
|
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
|
2023-03-05 00:10:55 +00:00 |
|
|
|
5705b8e8a5
|
Added support for Verilator!
|
2023-03-04 08:37:43 +00:00 |
|
|
|
cac01f0333
|
Fixed Makefile bug
|
2023-02-22 01:51:14 +00:00 |
|
|
|
7fde422341
|
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
|
2023-02-22 01:28:23 +00:00 |
|
|
|
e2e9a92832
|
Cleaned the decoder a bit and laid down some of the groundwork for microcode
|
2023-02-19 16:22:23 +00:00 |
|
|
|
fd4a9b5442
|
Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
|
2023-02-19 00:20:53 +00:00 |
|
|
|
82bd859874
|
Moved the decoding of opcodes into a separate module and optimised memory reads
|
2023-02-17 18:08:09 +00:00 |
|
|
|
ed3d7101d3
|
Further improved build system and changed brainfuck print message
|
2023-02-16 23:26:32 +00:00 |
|
|
|
ded47555a5
|
Improved build system and project directory structure
|
2023-02-16 01:52:02 +00:00 |
|
