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5feee9de57
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Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
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2023-11-02 00:29:14 +00:00 |
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021dd06e9a
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Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
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2023-05-19 17:59:20 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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5705b8e8a5
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Added support for Verilator!
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2023-03-04 08:37:43 +00:00 |
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b00cd988cf
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Cleaned up boot_code
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2023-03-03 19:36:28 +00:00 |
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619702384b
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Wrote an optimised native brainfuck compiler intended to be the default program running on release v0.1 utilising a good precentage of the 8086 instruction set
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2023-02-19 21:42:59 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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037f6dd7da
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Added support for writing to memory
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2023-02-14 13:13:40 +00:00 |
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d7eb4f36c0
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Wrote very basic brainfuck interpreter in 8086 asm to work on making it run and prove Turing completeness
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2023-02-11 01:12:54 +00:00 |
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fc4ecdb8d2
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Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing
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2023-02-10 18:21:19 +00:00 |
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19fcf11f63
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Still hadn't added all files from the assembler commit. Also fixed .gitignore
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2023-02-10 13:32:51 +00:00 |
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5371caa3bb
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Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
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2023-02-08 23:59:06 +00:00 |
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f9393cb69f
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Basic start for the control block
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2023-02-08 09:18:00 +00:00 |
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