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63ea29e399
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Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
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2023-12-03 19:24:39 +00:00 |
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29bc2e6d96
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Project: Cleaned up some code and run the project through aspell
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2023-11-15 14:37:46 +00:00 |
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01dcbfa7a1
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The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
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2023-11-06 08:13:36 +00:00 |
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df2975fa09
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Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
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2023-11-04 11:04:22 +00:00 |
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08aac5c7b6
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Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
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2023-11-02 22:19:15 +00:00 |
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1b510e4781
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Made the size of the cache variable
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2023-05-18 11:21:27 +01:00 |
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53e9d371d7
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Fully optimised BIU. Now it can instantly deliver instructions back to back
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2023-05-16 18:07:28 +01:00 |
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07d2a80b2e
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Added code to record statistics and a tool to plot them
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2023-05-14 16:06:33 +01:00 |
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539fb8416b
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Fixed copyright notices, did some major cleanup and bumped README's versions
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2023-05-11 16:28:10 +01:00 |
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b7bfbd4e33
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Improved BIU performance and debug messages
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2023-05-10 04:05:56 +01:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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