|
|
5feee9de57
|
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
|
2023-11-02 00:29:14 +00:00 |
|
|
|
b2972c9938
|
release v0.2.0 - Pipelined milestone
|
2023-11-01 06:08:12 +00:00 |
|
|
|
3ec90b1843
|
Added version stamp and last commit to json log
|
2023-11-01 06:03:53 +00:00 |
|
|
|
07d2a80b2e
|
Added code to record statistics and a tool to plot them
|
2023-05-14 16:06:33 +01:00 |
|
|
|
9de83fd7c1
|
Added partial support for the software interrupt INT instruction
|
2023-03-08 07:26:28 +00:00 |
|
|
|
8070d4e58a
|
Improved build system's handling of verilator
|
2023-03-05 23:11:18 +00:00 |
|
|
|
99cbc49e95
|
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
|
2023-03-05 00:10:55 +00:00 |
|
|
|
5705b8e8a5
|
Added support for Verilator!
|
2023-03-04 08:37:43 +00:00 |
|
|
|
6e8d951360
|
Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
|
2023-02-24 17:38:23 +00:00 |
|
|
|
cac01f0333
|
Fixed Makefile bug
|
2023-02-22 01:51:14 +00:00 |
|
|
|
e2e9a92832
|
Cleaned the decoder a bit and laid down some of the groundwork for microcode
|
2023-02-19 16:22:23 +00:00 |
|
|
|
82bd859874
|
Moved the decoding of opcodes into a separate module and optimised memory reads
|
2023-02-17 18:08:09 +00:00 |
|
|
|
ed3d7101d3
|
Further improved build system and changed brainfuck print message
|
2023-02-16 23:26:32 +00:00 |
|
|
|
ded47555a5
|
Improved build system and project directory structure
|
2023-02-16 01:52:02 +00:00 |
|
