1966ab78b4
Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
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I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
533f346f9b
Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
2023-12-07 16:39:04 +00:00
8c921380bc
Peripherals/BuiltinRam: Fixed high impedance warning in yosys
2023-12-04 17:04:22 +00:00
63ea29e399
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
2023-12-03 19:24:39 +00:00
aedefddb5d
Project: The cpu finally works perfectly now even at full speed as far as i can tell! I made the ram and register writes synchronous which fixed the weird issues I had, then I added -abc9 to yosys so that nextpnr can actually route the cpu at full speed and increased the display fifo since the cpu is so fast now!!
2023-11-15 18:43:56 +00:00
2c8e8a9d9c
Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
2023-11-12 21:39:27 +00:00
7d2cb5672f
Reduced numbers to be sorted in gnome_sort.asm to fit in lcd, fixed hlt on real hardware, slowed down cpu, increased lcd fifo and with that I almost got gnome_sort.asm working perfectly on real hardware
2023-11-12 07:31:05 +00:00
01dcbfa7a1
The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
2023-11-06 08:13:36 +00:00
43f3e16ca4
Removed all instances of inout since from what i understand it's mostly synthesisable
2023-11-02 21:48:12 +00:00
5feee9de57
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
e4ef199b83
Fixed a memory corruption bug
2023-05-10 08:35:14 +01:00
f4b22951d0
Cleaned up some pieces of code and fixed a bug
2023-05-04 00:49:04 +01:00
11624ca2d2
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
2023-03-09 06:03:13 +00:00
5705b8e8a5
Added support for Verilator!
2023-03-04 08:37:43 +00:00
f60084344e
Overhauled cpu frontend. Made memory byte addressable (necessary), cleaned up state machine and fixed small bug with MOV
2023-03-03 06:29:06 +00:00
6e8d951360
Increased the accessible memory and got the Mandelbrot renderer working under the brainfuck compiler!
2023-02-24 17:38:23 +00:00
fd4a9b5442
Fixed register addressing bug, mem read endianness, cleaned up code and added a provisional project logo
2023-02-19 00:20:53 +00:00
ded47555a5
Improved build system and project directory structure
2023-02-16 01:52:02 +00:00
