1966ab78b4
Peripherals/I2C: Added a CPU I2C driver and wrote a bootloader that uses that to boot from an I2C eeprom
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I'm happy to have reached 200 commits and with this, version v0.3.0 is functionally ready. I still need to do a fair bit of cleanup and bug fixing though before the actual release. With this commit I added a CPU I2C driver as well as a basic arbiter to have the hardware lcd controller and the software i2c communication pass through the same I2C driver and I2C bus. I also wrote a bootloader that reads code from an i2c eeprom to make sure the hardware works.
2024-02-09 23:30:58 +00:00
1d9be44c5a
Build system: renamed upload to upload_bitstream to allow for an upload_firmware in the future
2024-01-22 20:19:14 +00:00
65dfd21ef0
Peripherals/I2C_driver: Uncommented code to check for device acknowledgment
2023-12-09 00:53:52 +00:00
94bc6eba39
Build system: Added help text and target mrproper which also deletes downloaded source code
2023-12-08 22:10:11 +00:00
533f346f9b
Build system: Added the ability to simulate an FPGA SoC and fixed all the warning verilator gave of the code previously used only for synthesis.
2023-12-07 16:39:04 +00:00
48249e8051
Forgot to add some of the files for the previous commit
2023-12-06 18:38:32 +00:00
dd50114c07
Build system: fixed adherence to the Makefile QUIET variable
2023-12-04 23:09:13 +00:00
63ea29e399
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
2023-12-03 19:24:39 +00:00
2c8e8a9d9c
Added simple support for \n and \r on the HD44780 driver, increased the synthesised mem to fit brainfuck_compiled.asm and made it the default.
2023-11-12 21:39:27 +00:00
618c3102d8
Fixed some dependencies on the makefiles
2023-11-12 13:30:12 +00:00
01dcbfa7a1
The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
2023-11-06 08:13:36 +00:00
5feee9de57
Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
2023-11-02 00:29:14 +00:00
3dd2ff59ea
Added 2 more test programs, 2 new instructions and fixed a bug in CMP
2023-05-21 01:48:50 +01:00
021dd06e9a
Added support for some more instructions, fixed a bug in CMP and also added a program that uses them
2023-05-19 17:59:20 +01:00
11624ca2d2
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
2023-03-09 06:03:13 +00:00
9de83fd7c1
Added partial support for the software interrupt INT instruction
2023-03-08 07:26:28 +00:00
5705b8e8a5
Added support for Verilator!
2023-03-04 08:37:43 +00:00
b00cd988cf
Cleaned up boot_code
2023-03-03 19:36:28 +00:00
0c36e9d78c
Added message about compilation process on the compiler and fixed Makefile dependencies
2023-02-25 01:42:45 +00:00
cac01f0333
Fixed Makefile bug
2023-02-22 01:51:14 +00:00
7fde422341
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
2023-02-22 01:28:23 +00:00
e2e9a92832
Cleaned the decoder a bit and laid down some of the groundwork for microcode
2023-02-19 16:22:23 +00:00
ed3d7101d3
Further improved build system and changed brainfuck print message
2023-02-16 23:26:32 +00:00
ded47555a5
Improved build system and project directory structure
2023-02-16 01:52:02 +00:00
