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fd31eb704c
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Made the simulation stop at an unrecognised instruction or other error
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2023-02-11 01:05:19 +00:00 |
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fc4ecdb8d2
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Added HLT instruction, made testbench count total clock cycles and write memdump and fixed reset timing
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2023-02-10 18:21:19 +00:00 |
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39f55aa6c3
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Added unaligned access for instructions and data and fixed register file access
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2023-02-10 12:02:20 +00:00 |
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a5571fda12
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Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions!
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2023-02-09 20:17:15 +00:00 |
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a166efec9c
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Moved clock generator to the testbench
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2023-02-09 14:51:50 +00:00 |
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c3a2f5eb01
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Added primitive decode stage, improved state handling and fixed CIR register
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2023-02-09 14:46:21 +00:00 |
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5371caa3bb
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Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
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2023-02-08 23:59:06 +00:00 |
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139ec3c0c0
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Standardised indentation
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2023-02-08 12:09:21 +00:00 |
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61a403271c
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Added ROM, address and data buses and primitive program counter
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2023-02-08 11:57:22 +00:00 |
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f9393cb69f
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Basic start for the control block
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2023-02-08 09:18:00 +00:00 |
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