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Added 16bit unaligned register indirect writes, fixed some MOV bugs, clean up code names and data flow

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-02-15 01:28:02 +00:00
parent c3563457c5
commit f4d28cf4c8
6 changed files with 145 additions and 106 deletions
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3
cpu/Makefile
View File

@ -27,13 +27,14 @@ brainf: ${VVP} brainfuck.txt
.PHONY: run .PHONY: run
run: ${VVP} boot_code.txt run: ${VVP} boot_code.txt
vvp ${VVP} vvp ${VVP}
grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin
.PHONY: build .PHONY: build
build: ${VVP} build: ${VVP}
.PHONY: wave .PHONY: wave
wave: ${VVP} brainfuck.txt wave: ${VVP} brainfuck.txt
vvp ${VVP} -lxt2 +BOOT_CODE=brainfuck.txt vvp ${VVP} -lxt2 #+BOOT_CODE=brainfuck.txt
gtkwave test.lx2 gtkwave_savefile.gtkw gtkwave test.lx2 gtkwave_savefile.gtkw
grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin

2
cpu/boot_code.asm
View File

@ -9,4 +9,6 @@ inc AL
mov AX,#0x00FF mov AX,#0x00FF
inc ax inc ax
ADD AX,#0x2200 ADD AX,#0x2200
MOV SI,#0x0102
MOV [SI],AX
HLT HLT

3
cpu/brainfuck.asm
View File

@ -64,10 +64,9 @@ jz SKIP_CODE_BLOCK
MOV AX,SI MOV AX,SI
inc CX inc CX
inc CX inc CX
push SI
MOV SI,CX MOV SI,CX
mov [SI],AX mov [SI],AX
POP SI mov SI,AX
JMP INTERPRET JMP INTERPRET
SKIP_CODE_BLOCK: SKIP_CODE_BLOCK:

10
cpu/proc_state_def.v
View File

@ -52,5 +52,11 @@
`define PROC_MEMIO_PUT_UNALIGNED_DATA 5'b10110 `define PROC_MEMIO_PUT_UNALIGNED_DATA 5'b10110
`define PROC_MEMIO_PUT_BYTE 5'b10111 `define PROC_MEMIO_PUT_BYTE 5'b10111
`define PROC_MEMIO_PUT_BYTE_STOP_READ 5'b11110 /****/ `define PROC_MEMIO_PUT_BYTE_STOP_READ 5'b11110 /****/
`define PROC_MEMIO_PUT_BYTE_WRITE 5'b11111 /****/ `define PROC_MEMIO_WRITE_EXIT 5'b11111 /****/
`define PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE 5'b00101 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT 5'b01100 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT1 5'b01101 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2 5'b01110 /****/
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3 5'b01111
`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4 5'b11010
`define PROC_DE_LOAD_REG_TO_PARAM 5'b11011

225
cpu/processor.v
View File

@ -43,7 +43,7 @@ assign external_data_bus=read?data_bus_output_register:'hz;
reg [`PROC_STATE_BITS-1:0] state; reg [`PROC_STATE_BITS-1:0] state;
// Registers // Registers
reg [19:0] ProgCount; reg [19:0] ProgCount; /*TODO consider having single circuit to increment PC instead of having possible lots of adders all over the code*/
reg [15:0] CIR; reg [15:0] CIR;
reg [15:0] PARAM1; reg [15:0] PARAM1;
reg [15:0] PARAM2; reg [15:0] PARAM2;
@ -76,12 +76,6 @@ reg [15:0]FLAGS;
reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest
// Execution units
reg [1:0] in1_sel;
reg [1:0] in2_sel;
/* out_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
reg [2:0] out_sel;
/*** RESET LOGIC ***/ /*** RESET LOGIC ***/
always @(negedge reset) begin always @(negedge reset) begin
if (reset==0) begin if (reset==0) begin
@ -90,7 +84,6 @@ always @(negedge reset) begin
ProgCount=0;//TODO: Reset Vector ProgCount=0;//TODO: Reset Vector
HALT=0; HALT=0;
reg_write_we=1; reg_write_we=1;
reg_read_oe=1;
unaligned_access=0; unaligned_access=0;
ALU_1OE=1; ALU_1OE=1;
@(posedge reset) @(posedge reset)
@ -105,28 +98,40 @@ end
//Architectural Register file //Architectural Register file
reg [3:0] reg_write_addr; reg [3:0] reg_write_addr;
reg [15:0] reg_write_data; wire [15:0] reg_write_data;
reg reg_write_we; reg reg_write_we;
reg [3:0] reg_read_addr; reg [3:0] reg_read_port1_addr;
reg [15:0] reg_read_data; reg [15:0] reg_read_port1_data;
reg reg_read_oe; reg [1:0] reg_write_in_sel;
register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_addr,reg_read_data,reg_read_oe); mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX(
ALU_1O,
16'hz,
16'hz,
16'hz,
reg_write_in_sel,
reg_write_data);
register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_port1_addr,reg_read_port1_data);
/**** ALU 1 ******/
reg [1:0] in_alu1_sel1;
reg [1:0] in_alu1_sel2;
/* out_alu1_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */
reg [2:0] out_alu1_sel;
//ALU
mux4 #(.WIDTH(16)) MUX16_1A( mux4 #(.WIDTH(16)) MUX16_1A(
PARAM1, PARAM1,
reg_read_data, reg_read_port1_data,
{ProgCount[14:0],unaligned_access}, /*THAT'S NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/ {ProgCount[14:0],unaligned_access},
16'b0, 16'b0,
in1_sel, in_alu1_sel1,
ALU_1A); ALU_1A);
mux4 #(.WIDTH(16)) MUX16_1B( mux4 #(.WIDTH(16)) MUX16_1B(
PARAM2, PARAM2,
reg_read_data, reg_read_port1_data,
{ProgCount[14:0],unaligned_access}, /*THAT'S NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/ {ProgCount[14:0],unaligned_access},
16'b0, 16'b0,
in2_sel, in_alu1_sel2,
ALU_1B); ALU_1B);
wire [15:0] ALU_1A; wire [15:0] ALU_1A;
@ -134,8 +139,8 @@ wire [15:0] ALU_1B;
wire [15:0] ALU_1O; wire [15:0] ALU_1O;
reg [`ALU_OP_BITS-1:0]ALU_1OP; reg [`ALU_OP_BITS-1:0]ALU_1OP;
reg ALU_1OE; reg ALU_1OE;
wire [7:0] ALU_FLAGS; wire [7:0] ALU_1FLAGS;
ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_FLAGS,Wbit); ALU ALU1(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_1FLAGS,Wbit);
/*** Processor stages ***/ /*** Processor stages ***/
@ -160,7 +165,7 @@ always @(negedge clock) begin
state=`PROC_DE_STATE_ENTRY; state=`PROC_DE_STATE_ENTRY;
end end
`PROC_EX_STATE_EXIT:begin `PROC_EX_STATE_EXIT:begin
case(out_sel) /*TODO: use RM*/ case(out_alu1_sel) /*TODO: use RM*/
3'b000, 3'b000,
3'b001, 3'b001,
3'b010 : begin 3'b010 : begin
@ -183,14 +188,12 @@ always @(negedge clock) begin
end end
3'b100:begin 3'b100:begin
/*[SI]*/ /*[SI]*/
reg_read_addr=4'b1110; reg_read_port1_addr=4'b1110;
reg_read_oe=0;
state=`PROC_MEMIO_WRITE; state=`PROC_MEMIO_WRITE;
end end
3'b101:begin 3'b101:begin
/*[DI]*/ /*[DI]*/
reg_read_addr=4'b1111; reg_read_port1_addr=4'b1111;
reg_read_oe=0;
state=`PROC_MEMIO_WRITE; state=`PROC_MEMIO_WRITE;
end end
3'b110:begin 3'b110:begin
@ -199,8 +202,7 @@ always @(negedge clock) begin
end end
3'b111:begin 3'b111:begin
/*[BX]*/ /*[BX]*/
reg_read_addr=4'b1011; reg_read_port1_addr=4'b1011;
reg_read_oe=0;
state=`PROC_MEMIO_WRITE; state=`PROC_MEMIO_WRITE;
end end
endcase endcase
@ -227,17 +229,35 @@ always @(negedge clock) begin
state=`PROC_DE_LOAD_16_EXTRA_FETCH; state=`PROC_DE_LOAD_16_EXTRA_FETCH;
end end
`PROC_MEMIO_READ_SETADDR:begin `PROC_MEMIO_READ_SETADDR:begin
external_address_bus = {1'b0,reg_read_data[15:1]}; external_address_bus = {1'b0,reg_read_port1_data[15:1]};
state=reg_read_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA; state=reg_read_port1_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA;
end end
`PROC_MEMIO_PUT_BYTE:begin `PROC_MEMIO_PUT_BYTE:begin
BYTE_WRITE_TEMP_REG=external_data_bus; BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_BYTE_STOP_READ; state=`PROC_MEMIO_PUT_BYTE_STOP_READ;
end end
`PROC_MEMIO_PUT_BYTE_WRITE:begin `PROC_MEMIO_WRITE_EXIT:begin
write=0; write=0;
state=`PROC_IF_STATE_ENTRY; state=`PROC_IF_STATE_ENTRY;
end end
`PROC_MEMIO_PUT_ALIGNED_DATA:begin
read=1;
data_bus_output_register={ALU_1O[7:0],ALU_1O[15:8]};
state=`PROC_MEMIO_WRITE_EXIT;
end
`PROC_MEMIO_PUT_UNALIGNED_DATA:begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE;
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin
write=0;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2;
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3:begin
BYTE_WRITE_TEMP_REG=external_data_bus;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4;
end
endcase endcase
end end
@ -257,10 +277,10 @@ always @(posedge clock) begin
external_address_bus <= ProgCount; external_address_bus <= ProgCount;
read <= 0; read <= 0;
write <= 1; write <= 1;
reg_read_oe=1;
reg_write_we=1; reg_write_we=1;
ALU_1OE=1; ALU_1OE=1;
state=`PROC_IF_WRITE_CIR; state=`PROC_IF_WRITE_CIR;
reg_write_in_sel=2'b00;
end end
`PROC_IF_STATE_EXTRA_FETCH_SET:begin `PROC_IF_STATE_EXTRA_FETCH_SET:begin
external_address_bus <= ProgCount; external_address_bus <= ProgCount;
@ -283,12 +303,11 @@ always @(posedge clock) begin
else else
`start_aligning_instruction `start_aligning_instruction
MOD=2'b11; MOD=2'b11;
in1_sel=2'b00; in_alu1_sel1=2'b00;
in2_sel=2'b01; in_alu1_sel2=2'b01;
out_sel=3'b011; out_alu1_sel=3'b011;
reg_read_addr={CIR[8:8],3'b000}; reg_read_port1_addr={CIR[8:8],3'b000};
reg_write_addr={CIR[8:8],3'b000}; reg_write_addr={CIR[8:8],3'b000};
reg_read_oe=0;
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
if(CIR[8:8]==1) if(CIR[8:8]==1)
@ -310,12 +329,11 @@ always @(posedge clock) begin
`start_aligning_instruction `start_aligning_instruction
Wbit=CIR[8:8]; Wbit=CIR[8:8];
MOD=2'b11; MOD=2'b11;
in1_sel=2'b00; in_alu1_sel1=2'b00;
in2_sel=2'b01; in_alu1_sel2=2'b01;
out_sel={1'b0,CIR[7:6]}; out_alu1_sel={1'b0,CIR[7:6]};
reg_read_addr={CIR[8:8],CIR[2:0]}; reg_read_port1_addr={CIR[8:8],CIR[2:0]};
reg_write_addr={CIR[8:8],CIR[2:0]}; reg_write_addr={CIR[8:8],CIR[2:0]};
reg_read_oe=0;
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
state=`PROC_DE_LOAD_16_PARAM; state=`PROC_DE_LOAD_16_PARAM;
@ -340,9 +358,9 @@ always @(posedge clock) begin
else else
`start_aligning_instruction `start_aligning_instruction
MOD=2'b11; MOD=2'b11;
in1_sel=2'b00; in_alu1_sel1=2'b00;
in2_sel=2'b00; in_alu1_sel2=2'b00;
out_sel=3'b011; out_alu1_sel=3'b011;
reg_write_addr={1'b0,CIR[10:8]}; reg_write_addr={1'b0,CIR[10:8]};
PARAM1[7:0]=CIR[7:0]; PARAM1[7:0]=CIR[7:0];
PARAM2=0; PARAM2=0;
@ -359,9 +377,9 @@ always @(posedge clock) begin
else else
`start_aligning_instruction `start_aligning_instruction
MOD=2'b11; MOD=2'b11;
in1_sel=2'b00; in_alu1_sel1=2'b00;
in2_sel=2'b00; in_alu1_sel2=2'b00;
out_sel=3'b011; out_alu1_sel=3'b011;
reg_write_addr={1'b1,CIR[10:8]}; reg_write_addr={1'b1,CIR[10:8]};
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
@ -371,43 +389,42 @@ always @(posedge clock) begin
6'b100010 : begin 6'b100010 : begin
/* MOV - Reg/Mem to/from register */ /* MOV - Reg/Mem to/from register */
/* 1 0 0 0 1 0 D W | MOD REG REG | < DISP LO > | < DISP HI > |*/ /* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/
`start_aligning_instruction `start_aligning_instruction
MOD=CIR[7:6]; MOD=CIR[7:6];
RM=CIR[2:0]; RM=CIR[2:0];
Wbit=CIR[8:8]; Wbit=CIR[8:8];
MOD=CIR[7:6]; in_alu1_sel2=2'b00;
in2_sel=2'b00;
if(CIR[9:9] == 1)begin if(CIR[9:9] == 1)begin
/* Mem/Reg to reg */ /* Mem/Reg to reg */
if(MOD==2'b11)begin if(MOD==2'b11)begin
/*Reg to Reg*/ /*Reg to Reg*/
in1_sel=2'b01; in_alu1_sel1=2'b01;
reg_read_addr=CIR[2:0]; reg_read_port1_addr=CIR[2:0];
state=`PROC_EX_STATE_ENTRY; state=`PROC_EX_STATE_ENTRY;
reg_read_oe=0;
end else begin end else begin
/*Mem to Reg*/ /*Mem to Reg*/
in1_sel=2'b00; in_alu1_sel1=2'b00;
state=`RPOC_MEMIO_READ; state=`RPOC_MEMIO_READ;
end end
out_sel=3'b011; out_alu1_sel=3'b011;
reg_write_addr={Wbit,CIR[5:3]}; reg_write_addr={Wbit,CIR[5:3]};
end else begin end else begin
/* Reg to Mem/Reg */ /* Reg to Mem/Reg */
if(MOD==2'b11)begin if(MOD==2'b11)begin
/*Reg to Reg*/ /*Reg to Reg*/
out_sel=3'b011; in_alu1_sel1=2'b01;
out_alu1_sel=3'b011;
reg_write_addr={Wbit,CIR[2:0]}; reg_write_addr={Wbit,CIR[2:0]};
state=`PROC_EX_STATE_ENTRY; state=`PROC_EX_STATE_ENTRY;
end else begin end else begin
/*Reg to Mem*/ /*Reg to Mem*/
out_sel={1'b0,RM}; in_alu1_sel1=2'b00;
state=`PROC_MEMIO_WRITE; reg_read_port1_addr=CIR[5:3];
out_alu1_sel={1'b0,MOD};
state=`PROC_DE_LOAD_REG_TO_PARAM;
end end
reg_read_oe=0; reg_read_port1_addr={Wbit,CIR[5:3]};
in1_sel=2'b01;
reg_read_addr={Wbit,CIR[5:3]};
end end
ALU_1OE=0; ALU_1OE=0;
@ -424,14 +441,13 @@ always @(posedge clock) begin
/* | 0 1 0 0 0 REG | */ /* | 0 1 0 0 0 REG | */
`start_unaligning_instruction `start_unaligning_instruction
Wbit=1; Wbit=1;
in1_sel=2'b01; in_alu1_sel1=2'b01;
in2_sel=2'b00; in_alu1_sel2=2'b00;
out_sel=3'b011; out_alu1_sel=3'b011;
MOD=2'b11; MOD=2'b11;
PARAM2=1; PARAM2=1;
reg_read_addr={1'b1,CIR[10:8]}; reg_read_port1_addr={1'b1,CIR[10:8]};
reg_write_addr={1'b1,CIR[10:8]}; reg_write_addr={1'b1,CIR[10:8]};
reg_read_oe=0;
ALU_1OE=0; ALU_1OE=0;
if(CIR[11:11]==0) if(CIR[11:11]==0)
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
@ -450,15 +466,14 @@ always @(posedge clock) begin
Wbit=CIR[8:8]; Wbit=CIR[8:8];
MOD=CIR[7:6]; MOD=CIR[7:6];
RM=CIR[2:0]; RM=CIR[2:0];
in1_sel=(MOD==2'b11)? 2'b01 : 2'b00; in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00;
in2_sel=2'b00;/* number 1 */ in_alu1_sel2=2'b00;/* number 1 */
out_sel={1'b0,MOD}; out_alu1_sel={1'b0,MOD};
PARAM2=1; PARAM2=1;
/*in case MOD=11 */ /*in case MOD=11 */
reg_read_addr={1'b0,RM}; reg_read_port1_addr={1'b0,RM};
reg_write_addr={1'b0,RM}; reg_write_addr={1'b0,RM};
reg_read_oe=0;
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD; ALU_1OP=`ALU_OP_ADD;
@ -505,11 +520,10 @@ always @(posedge clock) begin
else else
`start_aligning_instruction `start_aligning_instruction
MOD=2'b11; MOD=2'b11;
in1_sel=2'b00; in_alu1_sel1=2'b00;
in2_sel=2'b01; in_alu1_sel2=2'b01;
reg_read_addr={CIR[8:8],3'b000}; reg_read_port1_addr={CIR[8:8],3'b000};
reg_read_oe=0; out_alu1_sel=3'b100;
out_sel=3'b100;
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_SUB; ALU_1OP=`ALU_OP_SUB;
if(CIR[8:8]==1) if(CIR[8:8]==1)
@ -536,12 +550,12 @@ always @(posedge clock) begin
/* .... */ /* .... */
`start_aligning_instruction `start_aligning_instruction
Wbit=1; Wbit=1;
in1_sel=2'b10; in_alu1_sel1=2'b10;
in2_sel=2'b00; in_alu1_sel2=2'b00;
PARAM2={{8{CIR[7:7]}},CIR[7:0]}; PARAM2={{8{CIR[7:7]}},CIR[7:0]};
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD_SIGNED_B; ALU_1OP=`ALU_OP_ADD_SIGNED_B;
out_sel=3'b101; out_alu1_sel=3'b101;
case(CIR[11:9]) case(CIR[11:9])
4'b000: begin 4'b000: begin
/* Jump on (not) Overflow */ /* Jump on (not) Overflow */
@ -598,13 +612,14 @@ always @(posedge clock) begin
2'b11: begin 2'b11: begin
/* JMP - Unconditional jump direct within segment (short) */ /* JMP - Unconditional jump direct within segment (short) */
/* | 1 1 1 0 1 0 0 1 | IP-INC-LO | */ /* | 1 1 1 0 1 0 0 1 | IP-INC-LO | */
`start_aligning_instruction
Wbit=1; Wbit=1;
in1_sel=2'b10; in_alu1_sel1=2'b10;
in2_sel=2'b00; in_alu1_sel2=2'b00;
PARAM2={{8{CIR[7:7]}},CIR[7:0]}; PARAM2={{8{CIR[7:7]}},CIR[7:0]};
ALU_1OE=0; ALU_1OE=0;
ALU_1OP=`ALU_OP_ADD_SIGNED_B; ALU_1OP=`ALU_OP_ADD_SIGNED_B;
out_sel=3'b101; out_alu1_sel=3'b101;
state=`PROC_EX_STATE_ENTRY; state=`PROC_EX_STATE_ENTRY;
end end
endcase endcase
@ -614,6 +629,10 @@ always @(posedge clock) begin
end end
endcase endcase
end end
`PROC_DE_LOAD_REG_TO_PARAM:begin
PARAM1=reg_read_port1_data;
state=`PROC_EX_STATE_ENTRY;
end
`PROC_DE_LOAD_16_PARAM:begin `PROC_DE_LOAD_16_PARAM:begin
if(unaligned_access==1)begin if(unaligned_access==1)begin
PARAM1[7:0] = external_data_bus[7:0]; PARAM1[7:0] = external_data_bus[7:0];
@ -651,14 +670,12 @@ always @(posedge clock) begin
end end
3'b100:begin 3'b100:begin
/*[SI]*/ /*[SI]*/
reg_read_addr=4'b1110; reg_read_port1_addr=4'b1110;
reg_read_oe=0;
state=`PROC_MEMIO_READ_SETADDR; state=`PROC_MEMIO_READ_SETADDR;
end end
3'b101:begin 3'b101:begin
/*[DI]*/ /*[DI]*/
reg_read_addr=4'b1111; reg_read_port1_addr=4'b1111;
reg_read_oe=0;
state=`PROC_MEMIO_READ_SETADDR; state=`PROC_MEMIO_READ_SETADDR;
end end
3'b110:begin 3'b110:begin
@ -667,8 +684,7 @@ always @(posedge clock) begin
end end
3'b111:begin 3'b111:begin
/*[BX]*/ /*[BX]*/
reg_read_addr=4'b1011; reg_read_port1_addr=4'b1011;
reg_read_oe=0;
state=`PROC_MEMIO_READ_SETADDR; state=`PROC_MEMIO_READ_SETADDR;
end end
endcase endcase
@ -691,22 +707,39 @@ always @(posedge clock) begin
end end
end end
`PROC_EX_STATE_ENTRY:begin `PROC_EX_STATE_ENTRY:begin
reg_write_data=ALU_1O; FLAGS[7:0] = ALU_1FLAGS[7:0];
FLAGS[7:0] = ALU_FLAGS[7:0];
state=`PROC_EX_STATE_EXIT; state=`PROC_EX_STATE_EXIT;
end end
`PROC_MEMIO_WRITE:begin `PROC_MEMIO_WRITE:begin
external_address_bus = {1'b0,reg_read_data[15:1]}; /* ADDRESS: reg_read_port1_data DATA:ALU1_O */
state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ; $display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O);
external_address_bus = {1'b0,reg_read_port1_data[15:1]};
state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ;
end end
`PROC_MEMIO_PUT_BYTE_STOP_READ:begin `PROC_MEMIO_PUT_BYTE_STOP_READ:begin
read=1; read=1;
state=`PROC_MEMIO_PUT_BYTE_WRITE; state=`PROC_MEMIO_WRITE_EXIT;
if(reg_read_data[0:0]==0) if(reg_read_port1_data[0:0]==0)
data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]}; data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]};
else else
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]}; data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end end
`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE:begin
read=1;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT;
data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]};
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin
external_address_bus=external_address_bus+1;
write=1;
read=0;
state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3;
end
`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4:begin
read=1;
state=`PROC_MEMIO_WRITE_EXIT;
data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]};
end
endcase endcase
end end

8
cpu/registers.v
View File

@ -21,18 +21,16 @@
/* Register address format: /* Register address format:
* [W-bit] [ 3-bit address] */ * [W-bit] [ 3-bit address] */
module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data,read_port1_oe); module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data);
input [3:0] write_port1_addr,read_port1_addr; input [3:0] write_port1_addr,read_port1_addr;
input [15:0] write_port1_data; input [15:0] write_port1_data;
output [15:0] read_port1_data; output [15:0] read_port1_data;
input read_port1_oe;
input write_port1_we; input write_port1_we;
reg [15:0] registers [7:0]; reg [15:0] registers [7:0];
assign read_port1_data = !read_port1_oe ? assign read_port1_data = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] : ( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) );
( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz;
`ifdef DEBUG_REG_WRITES `ifdef DEBUG_REG_WRITES
string debug_name; string debug_name;