diff --git a/cpu/Makefile b/cpu/Makefile index a82df3c..95900f0 100644 --- a/cpu/Makefile +++ b/cpu/Makefile @@ -27,13 +27,14 @@ brainf: ${VVP} brainfuck.txt .PHONY: run run: ${VVP} boot_code.txt vvp ${VVP} + grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin .PHONY: build build: ${VVP} .PHONY: wave wave: ${VVP} brainfuck.txt - vvp ${VVP} -lxt2 +BOOT_CODE=brainfuck.txt + vvp ${VVP} -lxt2 #+BOOT_CODE=brainfuck.txt gtkwave test.lx2 gtkwave_savefile.gtkw grep -v '^//' memdump.txt | xxd -ps -c 2 -r > memdump.bin diff --git a/cpu/boot_code.asm b/cpu/boot_code.asm index 1f66123..8fcc1b0 100644 --- a/cpu/boot_code.asm +++ b/cpu/boot_code.asm @@ -9,4 +9,6 @@ inc AL mov AX,#0x00FF inc ax ADD AX,#0x2200 +MOV SI,#0x0102 +MOV [SI],AX HLT diff --git a/cpu/brainfuck.asm b/cpu/brainfuck.asm index 8663bfc..9f76534 100644 --- a/cpu/brainfuck.asm +++ b/cpu/brainfuck.asm @@ -64,10 +64,9 @@ jz SKIP_CODE_BLOCK MOV AX,SI inc CX inc CX -push SI MOV SI,CX mov [SI],AX -POP SI +mov SI,AX JMP INTERPRET SKIP_CODE_BLOCK: diff --git a/cpu/proc_state_def.v b/cpu/proc_state_def.v index 5572fa5..e0ed648 100644 --- a/cpu/proc_state_def.v +++ b/cpu/proc_state_def.v @@ -52,5 +52,11 @@ `define PROC_MEMIO_PUT_UNALIGNED_DATA 5'b10110 `define PROC_MEMIO_PUT_BYTE 5'b10111 `define PROC_MEMIO_PUT_BYTE_STOP_READ 5'b11110 /****/ -`define PROC_MEMIO_PUT_BYTE_WRITE 5'b11111 /****/ - +`define PROC_MEMIO_WRITE_EXIT 5'b11111 /****/ +`define PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE 5'b00101 /****/ +`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT 5'b01100 /****/ +`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT1 5'b01101 /****/ +`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2 5'b01110 /****/ +`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3 5'b01111 +`define PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4 5'b11010 +`define PROC_DE_LOAD_REG_TO_PARAM 5'b11011 diff --git a/cpu/processor.v b/cpu/processor.v index 9453ca2..e4ee71f 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -43,7 +43,7 @@ assign external_data_bus=read?data_bus_output_register:'hz; reg [`PROC_STATE_BITS-1:0] state; // Registers -reg [19:0] ProgCount; +reg [19:0] ProgCount; /*TODO consider having single circuit to increment PC instead of having possible lots of adders all over the code*/ reg [15:0] CIR; reg [15:0] PARAM1; reg [15:0] PARAM2; @@ -76,12 +76,6 @@ reg [15:0]FLAGS; reg [15:0] BYTE_WRITE_TEMP_REG;//we read 16bits here if we want to change just 8 and leave the rest -// Execution units -reg [1:0] in1_sel; -reg [1:0] in2_sel; -/* out_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */ -reg [2:0] out_sel; - /*** RESET LOGIC ***/ always @(negedge reset) begin if (reset==0) begin @@ -90,7 +84,6 @@ always @(negedge reset) begin ProgCount=0;//TODO: Reset Vector HALT=0; reg_write_we=1; - reg_read_oe=1; unaligned_access=0; ALU_1OE=1; @(posedge reset) @@ -105,28 +98,40 @@ end //Architectural Register file reg [3:0] reg_write_addr; -reg [15:0] reg_write_data; +wire [15:0] reg_write_data; reg reg_write_we; -reg [3:0] reg_read_addr; -reg [15:0] reg_read_data; -reg reg_read_oe; -register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_addr,reg_read_data,reg_read_oe); +reg [3:0] reg_read_port1_addr; +reg [15:0] reg_read_port1_data; +reg [1:0] reg_write_in_sel; +mux4 #(.WIDTH(16)) REG_FILE_WRITE_IN_MUX( + ALU_1O, + 16'hz, + 16'hz, + 16'hz, + reg_write_in_sel, + reg_write_data); +register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_port1_addr,reg_read_port1_data); + +/**** ALU 1 ******/ +reg [1:0] in_alu1_sel1; +reg [1:0] in_alu1_sel2; +/* out_alu1_sel : { EXTRA_FUNCTIONS_BIT[0:0], MOD_OR_EXTRA_FUNCTION[1:0] } */ +reg [2:0] out_alu1_sel; -//ALU mux4 #(.WIDTH(16)) MUX16_1A( PARAM1, - reg_read_data, - {ProgCount[14:0],unaligned_access}, /*THAT'S NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/ + reg_read_port1_data, + {ProgCount[14:0],unaligned_access}, 16'b0, - in1_sel, + in_alu1_sel1, ALU_1A); mux4 #(.WIDTH(16)) MUX16_1B( PARAM2, - reg_read_data, - {ProgCount[14:0],unaligned_access}, /*THAT'S NOT ALL OF ADDR Bus, is that irrelevant with segmentation??*/ + reg_read_port1_data, + {ProgCount[14:0],unaligned_access}, 16'b0, - in2_sel, + in_alu1_sel2, ALU_1B); wire [15:0] ALU_1A; @@ -134,8 +139,8 @@ wire [15:0] ALU_1B; wire [15:0] ALU_1O; reg [`ALU_OP_BITS-1:0]ALU_1OP; reg ALU_1OE; -wire [7:0] ALU_FLAGS; -ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_FLAGS,Wbit); +wire [7:0] ALU_1FLAGS; +ALU ALU1(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP,ALU_1FLAGS,Wbit); /*** Processor stages ***/ @@ -160,7 +165,7 @@ always @(negedge clock) begin state=`PROC_DE_STATE_ENTRY; end `PROC_EX_STATE_EXIT:begin - case(out_sel) /*TODO: use RM*/ + case(out_alu1_sel) /*TODO: use RM*/ 3'b000, 3'b001, 3'b010 : begin @@ -183,14 +188,12 @@ always @(negedge clock) begin end 3'b100:begin /*[SI]*/ - reg_read_addr=4'b1110; - reg_read_oe=0; + reg_read_port1_addr=4'b1110; state=`PROC_MEMIO_WRITE; end 3'b101:begin /*[DI]*/ - reg_read_addr=4'b1111; - reg_read_oe=0; + reg_read_port1_addr=4'b1111; state=`PROC_MEMIO_WRITE; end 3'b110:begin @@ -199,8 +202,7 @@ always @(negedge clock) begin end 3'b111:begin /*[BX]*/ - reg_read_addr=4'b1011; - reg_read_oe=0; + reg_read_port1_addr=4'b1011; state=`PROC_MEMIO_WRITE; end endcase @@ -227,17 +229,35 @@ always @(negedge clock) begin state=`PROC_DE_LOAD_16_EXTRA_FETCH; end `PROC_MEMIO_READ_SETADDR:begin - external_address_bus = {1'b0,reg_read_data[15:1]}; - state=reg_read_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA; + external_address_bus = {1'b0,reg_read_port1_data[15:1]}; + state=reg_read_port1_data[0:0]?`PROC_MEMIO_GET_UNALIGNED_DATA:`PROC_MEMIO_GET_ALIGNED_DATA; end `PROC_MEMIO_PUT_BYTE:begin BYTE_WRITE_TEMP_REG=external_data_bus; state=`PROC_MEMIO_PUT_BYTE_STOP_READ; end - `PROC_MEMIO_PUT_BYTE_WRITE:begin + `PROC_MEMIO_WRITE_EXIT:begin write=0; state=`PROC_IF_STATE_ENTRY; end + `PROC_MEMIO_PUT_ALIGNED_DATA:begin + read=1; + data_bus_output_register={ALU_1O[7:0],ALU_1O[15:8]}; + state=`PROC_MEMIO_WRITE_EXIT; + end + `PROC_MEMIO_PUT_UNALIGNED_DATA:begin + BYTE_WRITE_TEMP_REG=external_data_bus; + state=`PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE; + end + `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT:begin + write=0; + state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2; + data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]}; + end + `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3:begin + BYTE_WRITE_TEMP_REG=external_data_bus; + state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4; + end endcase end @@ -257,10 +277,10 @@ always @(posedge clock) begin external_address_bus <= ProgCount; read <= 0; write <= 1; - reg_read_oe=1; reg_write_we=1; ALU_1OE=1; state=`PROC_IF_WRITE_CIR; + reg_write_in_sel=2'b00; end `PROC_IF_STATE_EXTRA_FETCH_SET:begin external_address_bus <= ProgCount; @@ -283,12 +303,11 @@ always @(posedge clock) begin else `start_aligning_instruction MOD=2'b11; - in1_sel=2'b00; - in2_sel=2'b01; - out_sel=3'b011; - reg_read_addr={CIR[8:8],3'b000}; + in_alu1_sel1=2'b00; + in_alu1_sel2=2'b01; + out_alu1_sel=3'b011; + reg_read_port1_addr={CIR[8:8],3'b000}; reg_write_addr={CIR[8:8],3'b000}; - reg_read_oe=0; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD; if(CIR[8:8]==1) @@ -310,12 +329,11 @@ always @(posedge clock) begin `start_aligning_instruction Wbit=CIR[8:8]; MOD=2'b11; - in1_sel=2'b00; - in2_sel=2'b01; - out_sel={1'b0,CIR[7:6]}; - reg_read_addr={CIR[8:8],CIR[2:0]}; + in_alu1_sel1=2'b00; + in_alu1_sel2=2'b01; + out_alu1_sel={1'b0,CIR[7:6]}; + reg_read_port1_addr={CIR[8:8],CIR[2:0]}; reg_write_addr={CIR[8:8],CIR[2:0]}; - reg_read_oe=0; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD; state=`PROC_DE_LOAD_16_PARAM; @@ -340,9 +358,9 @@ always @(posedge clock) begin else `start_aligning_instruction MOD=2'b11; - in1_sel=2'b00; - in2_sel=2'b00; - out_sel=3'b011; + in_alu1_sel1=2'b00; + in_alu1_sel2=2'b00; + out_alu1_sel=3'b011; reg_write_addr={1'b0,CIR[10:8]}; PARAM1[7:0]=CIR[7:0]; PARAM2=0; @@ -359,9 +377,9 @@ always @(posedge clock) begin else `start_aligning_instruction MOD=2'b11; - in1_sel=2'b00; - in2_sel=2'b00; - out_sel=3'b011; + in_alu1_sel1=2'b00; + in_alu1_sel2=2'b00; + out_alu1_sel=3'b011; reg_write_addr={1'b1,CIR[10:8]}; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD; @@ -371,43 +389,42 @@ always @(posedge clock) begin 6'b100010 : begin /* MOV - Reg/Mem to/from register */ - /* 1 0 0 0 1 0 D W | MOD REG REG | < DISP LO > | < DISP HI > |*/ + /* 1 0 0 0 1 0 D W | MOD REG RM | < DISP LO > | < DISP HI > |*/ `start_aligning_instruction MOD=CIR[7:6]; RM=CIR[2:0]; Wbit=CIR[8:8]; - MOD=CIR[7:6]; - in2_sel=2'b00; + in_alu1_sel2=2'b00; if(CIR[9:9] == 1)begin /* Mem/Reg to reg */ if(MOD==2'b11)begin /*Reg to Reg*/ - in1_sel=2'b01; - reg_read_addr=CIR[2:0]; + in_alu1_sel1=2'b01; + reg_read_port1_addr=CIR[2:0]; state=`PROC_EX_STATE_ENTRY; - reg_read_oe=0; end else begin /*Mem to Reg*/ - in1_sel=2'b00; + in_alu1_sel1=2'b00; state=`RPOC_MEMIO_READ; end - out_sel=3'b011; + out_alu1_sel=3'b011; reg_write_addr={Wbit,CIR[5:3]}; end else begin /* Reg to Mem/Reg */ if(MOD==2'b11)begin /*Reg to Reg*/ - out_sel=3'b011; + in_alu1_sel1=2'b01; + out_alu1_sel=3'b011; reg_write_addr={Wbit,CIR[2:0]}; state=`PROC_EX_STATE_ENTRY; end else begin /*Reg to Mem*/ - out_sel={1'b0,RM}; - state=`PROC_MEMIO_WRITE; + in_alu1_sel1=2'b00; + reg_read_port1_addr=CIR[5:3]; + out_alu1_sel={1'b0,MOD}; + state=`PROC_DE_LOAD_REG_TO_PARAM; end - reg_read_oe=0; - in1_sel=2'b01; - reg_read_addr={Wbit,CIR[5:3]}; + reg_read_port1_addr={Wbit,CIR[5:3]}; end ALU_1OE=0; @@ -424,14 +441,13 @@ always @(posedge clock) begin /* | 0 1 0 0 0 REG | */ `start_unaligning_instruction Wbit=1; - in1_sel=2'b01; - in2_sel=2'b00; - out_sel=3'b011; + in_alu1_sel1=2'b01; + in_alu1_sel2=2'b00; + out_alu1_sel=3'b011; MOD=2'b11; PARAM2=1; - reg_read_addr={1'b1,CIR[10:8]}; + reg_read_port1_addr={1'b1,CIR[10:8]}; reg_write_addr={1'b1,CIR[10:8]}; - reg_read_oe=0; ALU_1OE=0; if(CIR[11:11]==0) ALU_1OP=`ALU_OP_ADD; @@ -450,15 +466,14 @@ always @(posedge clock) begin Wbit=CIR[8:8]; MOD=CIR[7:6]; RM=CIR[2:0]; - in1_sel=(MOD==2'b11)? 2'b01 : 2'b00; - in2_sel=2'b00;/* number 1 */ - out_sel={1'b0,MOD}; + in_alu1_sel1=(MOD==2'b11)? 2'b01 : 2'b00; + in_alu1_sel2=2'b00;/* number 1 */ + out_alu1_sel={1'b0,MOD}; PARAM2=1; /*in case MOD=11 */ - reg_read_addr={1'b0,RM}; + reg_read_port1_addr={1'b0,RM}; reg_write_addr={1'b0,RM}; - reg_read_oe=0; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD; @@ -505,11 +520,10 @@ always @(posedge clock) begin else `start_aligning_instruction MOD=2'b11; - in1_sel=2'b00; - in2_sel=2'b01; - reg_read_addr={CIR[8:8],3'b000}; - reg_read_oe=0; - out_sel=3'b100; + in_alu1_sel1=2'b00; + in_alu1_sel2=2'b01; + reg_read_port1_addr={CIR[8:8],3'b000}; + out_alu1_sel=3'b100; ALU_1OE=0; ALU_1OP=`ALU_OP_SUB; if(CIR[8:8]==1) @@ -536,12 +550,12 @@ always @(posedge clock) begin /* .... */ `start_aligning_instruction Wbit=1; - in1_sel=2'b10; - in2_sel=2'b00; + in_alu1_sel1=2'b10; + in_alu1_sel2=2'b00; PARAM2={{8{CIR[7:7]}},CIR[7:0]}; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD_SIGNED_B; - out_sel=3'b101; + out_alu1_sel=3'b101; case(CIR[11:9]) 4'b000: begin /* Jump on (not) Overflow */ @@ -598,13 +612,14 @@ always @(posedge clock) begin 2'b11: begin /* JMP - Unconditional jump direct within segment (short) */ /* | 1 1 1 0 1 0 0 1 | IP-INC-LO | */ + `start_aligning_instruction Wbit=1; - in1_sel=2'b10; - in2_sel=2'b00; + in_alu1_sel1=2'b10; + in_alu1_sel2=2'b00; PARAM2={{8{CIR[7:7]}},CIR[7:0]}; ALU_1OE=0; ALU_1OP=`ALU_OP_ADD_SIGNED_B; - out_sel=3'b101; + out_alu1_sel=3'b101; state=`PROC_EX_STATE_ENTRY; end endcase @@ -614,6 +629,10 @@ always @(posedge clock) begin end endcase end + `PROC_DE_LOAD_REG_TO_PARAM:begin + PARAM1=reg_read_port1_data; + state=`PROC_EX_STATE_ENTRY; + end `PROC_DE_LOAD_16_PARAM:begin if(unaligned_access==1)begin PARAM1[7:0] = external_data_bus[7:0]; @@ -651,14 +670,12 @@ always @(posedge clock) begin end 3'b100:begin /*[SI]*/ - reg_read_addr=4'b1110; - reg_read_oe=0; + reg_read_port1_addr=4'b1110; state=`PROC_MEMIO_READ_SETADDR; end 3'b101:begin /*[DI]*/ - reg_read_addr=4'b1111; - reg_read_oe=0; + reg_read_port1_addr=4'b1111; state=`PROC_MEMIO_READ_SETADDR; end 3'b110:begin @@ -667,8 +684,7 @@ always @(posedge clock) begin end 3'b111:begin /*[BX]*/ - reg_read_addr=4'b1011; - reg_read_oe=0; + reg_read_port1_addr=4'b1011; state=`PROC_MEMIO_READ_SETADDR; end endcase @@ -691,22 +707,39 @@ always @(posedge clock) begin end end `PROC_EX_STATE_ENTRY:begin - reg_write_data=ALU_1O; - FLAGS[7:0] = ALU_FLAGS[7:0]; + FLAGS[7:0] = ALU_1FLAGS[7:0]; state=`PROC_EX_STATE_EXIT; end `PROC_MEMIO_WRITE:begin - external_address_bus = {1'b0,reg_read_data[15:1]}; - state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ; + /* ADDRESS: reg_read_port1_data DATA:ALU1_O */ + $display("Writing at %04x , %04x",reg_read_port1_data,ALU_1O); + external_address_bus = {1'b0,reg_read_port1_data[15:1]}; + state = (Wbit==0) ? `PROC_MEMIO_PUT_BYTE : (reg_read_port1_data[0:0]?`PROC_MEMIO_PUT_UNALIGNED_DATA:`PROC_MEMIO_PUT_ALIGNED_DATA) ; end `PROC_MEMIO_PUT_BYTE_STOP_READ:begin read=1; - state=`PROC_MEMIO_PUT_BYTE_WRITE; - if(reg_read_data[0:0]==0) + state=`PROC_MEMIO_WRITE_EXIT; + if(reg_read_port1_data[0:0]==0) data_bus_output_register={ALU_1O[7:0],BYTE_WRITE_TEMP_REG[7:0]}; else data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]}; end + `PROC_MEMIO_PUT_UNALIGNED_FIRST_BYTE:begin + read=1; + state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT; + data_bus_output_register={BYTE_WRITE_TEMP_REG[15:8],ALU_1O[7:0]}; + end + `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT2:begin + external_address_bus=external_address_bus+1; + write=1; + read=0; + state=`PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT3; + end + `PROC_MEMIO_PUT_UNALIGNED_PREP_NEXT4:begin + read=1; + state=`PROC_MEMIO_WRITE_EXIT; + data_bus_output_register={ALU_1O[15:8],BYTE_WRITE_TEMP_REG[7:0]}; + end endcase end diff --git a/cpu/registers.v b/cpu/registers.v index d12ad0c..c5d0139 100644 --- a/cpu/registers.v +++ b/cpu/registers.v @@ -21,18 +21,16 @@ /* Register address format: * [W-bit] [ 3-bit address] */ -module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data,read_port1_oe); +module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data); input [3:0] write_port1_addr,read_port1_addr; input [15:0] write_port1_data; output [15:0] read_port1_data; -input read_port1_oe; input write_port1_we; reg [15:0] registers [7:0]; -assign read_port1_data = !read_port1_oe ? - ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] : - ( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ) : 'hz; +assign read_port1_data = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] : + ( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) ); `ifdef DEBUG_REG_WRITES string debug_name;