75 lines
2.3 KiB
Verilog
75 lines
2.3 KiB
Verilog
/* registers.v - implementation of the architectural register file for the 9086 CPU
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "config.v"
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/* Register address format:
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* [W-bit] [ 3-bit address] */
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module register_file (write_port1_addr,write_port1_data,write_port1_we,read_port1_addr,read_port1_data);
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input [3:0] write_port1_addr,read_port1_addr;
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input [15:0] write_port1_data;
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output [15:0] read_port1_data;
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input write_port1_we;
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reg [15:0] registers [7:0];
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assign read_port1_data = ( read_port1_addr[3:3] ? registers[read_port1_addr[2:0]] :
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( read_port1_addr[2:2] ? {8'b0,registers[read_port1_addr[2:0]][15:8]} : {8'b0,registers[read_port1_addr[2:0]][7:0]} ) );
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`ifdef DEBUG_REG_WRITES
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string debug_name;
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`endif
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always @(negedge write_port1_we) begin
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if(write_port1_addr[3:3]==1)begin
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/* Word : AX,CX,DX,BX,SP,BP,SI,DI */
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registers[write_port1_addr[2:0]]=write_port1_data;
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end else begin
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/* Byte : AL,CL,DL,BL,AX,CX,DX,BX */
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if(write_port1_addr[2:2]==1)begin
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/* Byte */
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registers[write_port1_addr[2:0]][15:8]=write_port1_data[7:0];
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end else begin
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/* Byte */
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registers[write_port1_addr[2:0]][7:0]=write_port1_data[7:0];
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end
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end
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`ifdef DEBUG_REG_WRITES
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if(write_port1_addr[3:2]==2'b11)begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="sp";
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2'b01: debug_name="bp";
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2'b10: debug_name="si";
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2'b11: debug_name="di";
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endcase
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end else begin
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case(write_port1_addr[1:0])
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2'b00: debug_name="ax";
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2'b01: debug_name="cx";
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2'b10: debug_name="dx";
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2'b11: debug_name="bx";
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endcase
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end
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$display("register %%%s update to $0x%04x",debug_name,registers[write_port1_addr[2:0]]);
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`endif
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end
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endmodule
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