Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
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@ -23,35 +23,38 @@ module fpga_top(
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input clk48,
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input user_button,
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output reset_n,
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// output reset_n,
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output reg rgb_led0_r,
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output reg rgb_led0_g,
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output reg rgb_led0_b,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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);
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wire HALT;
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wire [`ERROR_BITS-1:0]ERROR;
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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system system(
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/* MISC */ clk48,user_button,HALT,ERROR
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/* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM
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/* MISC */ clk48,user_button
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/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
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);
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reg [2:0]rgb_led_color;
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assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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always @(HALT or ERROR or user_button) begin
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if (HALT==0) begin
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/* yellow */
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rgb_led_r=0;
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rgb_led_g=0;
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rgb_led_b=1;
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rgb_led_color<=3'b100;
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end else if (ERROR != `ERROR_BITS'b0) begin
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/* red */
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rgb_led_r=0;
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rgb_led_g=1;
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rgb_led_b=1;
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rgb_led_color<=3'b110;
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end else begin
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rgb_led_r=1;
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rgb_led_g=0;
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rgb_led_b=1;
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/* green */
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rgb_led_color<=3'b101;
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end
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end
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@ -61,7 +61,7 @@ string waveform_name;
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`endif
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initial begin
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`ifndef YOSYS
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`ifndef SYNTHESIS
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p,cycles);
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@ -76,9 +76,9 @@ initial begin
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end else
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json_file_descriptor=0;
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`endif
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`endif
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sane=0;
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finish=0;
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`endif
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end
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//integer killswitch=0;
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@ -193,11 +193,8 @@ reg [128:0] instruction_count_temp;
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finish<=2'd1;
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end
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end
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`endif
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always @(negedge clock)begin
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always @(negedge clock)begin
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if(reset==1)
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cycles<=cycles+1;
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else begin
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@ -206,7 +203,9 @@ always @(negedge clock)begin
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instruction_count <= 0;
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`endif
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end
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end
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end
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`endif
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endmodule
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