diff --git a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
index 4a721f2..fd65a57 100644
--- a/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
+++ b/system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
@@ -23,35 +23,38 @@ module fpga_top(
 	input clk48,
 
 	input user_button,
-	output reset_n,
+//	output reset_n,
 
-	output reg rgb_led0_r,
-	output reg rgb_led0_g,
-	output reg rgb_led0_b,
+	output rgb_led0_r,
+	output rgb_led0_g,
+	output rgb_led0_b,
 );
 
 wire HALT;
 wire [`ERROR_BITS-1:0]ERROR;
+wire [19:0] address_bus;
+wire [15:0] data_bus_read,data_bus_write;
+wire rd,wr,BHE,IOMEM;
 system system(
-	/*     MISC    */ clk48,user_button,HALT,ERROR
-	/* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM
+	/*     MISC    */ clk48,user_button
+	/* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
 );
 
+reg [2:0]rgb_led_color;
+assign rgb_led0_r=rgb_led_color[0];
+assign rgb_led0_g=rgb_led_color[1];
+assign rgb_led0_b=rgb_led_color[2];
+
 always @(HALT or ERROR or user_button) begin
 	if (HALT==0) begin
 		/* yellow */
-		rgb_led_r=0;
-		rgb_led_g=0;
-		rgb_led_b=1;
+		rgb_led_color<=3'b100;
 	end else if (ERROR != `ERROR_BITS'b0) begin
 		/* red */
-		rgb_led_r=0;
-		rgb_led_g=1;
-		rgb_led_b=1;
+		rgb_led_color<=3'b110;
 	end else begin
-		rgb_led_r=1;
-		rgb_led_g=0;
-		rgb_led_b=1;
+		/* green */
+		rgb_led_color<=3'b101;
 	end
 end
 
diff --git a/system/system.v b/system/system.v
index 2344027..dd37275 100644
--- a/system/system.v
+++ b/system/system.v
@@ -61,7 +61,7 @@ string waveform_name;
 `endif
 
 initial begin
-	`ifndef YOSYS
+	`ifndef SYNTHESIS
 		if($value$plusargs("WAVEFORM=%s",waveform_name))begin
 			$dumpfile(waveform_name);
 			$dumpvars(0,p,cycles);
@@ -76,9 +76,9 @@ initial begin
 		end else
 			json_file_descriptor=0;
 		`endif
+		sane=0;
+		finish=0;
 	`endif
-	sane=0;
-	finish=0;
 end
 
 //integer killswitch=0;
@@ -193,20 +193,19 @@ reg [128:0] instruction_count_temp;
 				finish<=2'd1;
 		end
 	end
+
+	always @(negedge clock)begin
+		if(reset==1)
+			cycles<=cycles+1;
+		else begin
+			cycles<=0;
+			`ifdef OTUPUT_JSON_STATISTICS
+			instruction_count <= 0;
+			`endif
+		end
+	end
 `endif
 
 
 
-always @(negedge clock)begin
-	if(reset==1)
-		cycles<=cycles+1;
-	else begin
-		cycles<=0;
-		`ifdef OTUPUT_JSON_STATISTICS
-		instruction_count <= 0;
-		`endif
-	end
-end
-
-
 endmodule