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Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code

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(Tim) Efthimis Kritikos 2023-11-02 23:46:12 +00:00
parent 08aac5c7b6
commit 934e2f5a36
2 changed files with 32 additions and 30 deletions
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33
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
View File

@ -23,35 +23,38 @@ module fpga_top(
input clk48, input clk48,
input user_button, input user_button,
output reset_n, // output reset_n,
output reg rgb_led0_r, output rgb_led0_r,
output reg rgb_led0_g, output rgb_led0_g,
output reg rgb_led0_b, output rgb_led0_b,
); );
wire HALT; wire HALT;
wire [`ERROR_BITS-1:0]ERROR; wire [`ERROR_BITS-1:0]ERROR;
wire [19:0] address_bus;
wire [15:0] data_bus_read,data_bus_write;
wire rd,wr,BHE,IOMEM;
system system( system system(
/* MISC */ clk48,user_button,HALT,ERROR /* MISC */ clk48,user_button
/* MEMORY / IO */ ,address_bus,data_bus,rd,wr,BHE,IOMEM /* MEMORY / IO */ ,address_bus,data_bus_read,data_bus_write,BHE,rd,wr,IOMEM,HALT,ERROR
); );
reg [2:0]rgb_led_color;
assign rgb_led0_r=rgb_led_color[0];
assign rgb_led0_g=rgb_led_color[1];
assign rgb_led0_b=rgb_led_color[2];
always @(HALT or ERROR or user_button) begin always @(HALT or ERROR or user_button) begin
if (HALT==0) begin if (HALT==0) begin
/* yellow */ /* yellow */
rgb_led_r=0; rgb_led_color<=3'b100;
rgb_led_g=0;
rgb_led_b=1;
end else if (ERROR != `ERROR_BITS'b0) begin end else if (ERROR != `ERROR_BITS'b0) begin
/* red */ /* red */
rgb_led_r=0; rgb_led_color<=3'b110;
rgb_led_g=1;
rgb_led_b=1;
end else begin end else begin
rgb_led_r=1; /* green */
rgb_led_g=0; rgb_led_color<=3'b101;
rgb_led_b=1;
end end
end end

13
system/system.v
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@ -61,7 +61,7 @@ string waveform_name;
`endif `endif
initial begin initial begin
`ifndef YOSYS `ifndef SYNTHESIS
if($value$plusargs("WAVEFORM=%s",waveform_name))begin if($value$plusargs("WAVEFORM=%s",waveform_name))begin
$dumpfile(waveform_name); $dumpfile(waveform_name);
$dumpvars(0,p,cycles); $dumpvars(0,p,cycles);
@ -76,9 +76,9 @@ initial begin
end else end else
json_file_descriptor=0; json_file_descriptor=0;
`endif `endif
`endif
sane=0; sane=0;
finish=0; finish=0;
`endif
end end
//integer killswitch=0; //integer killswitch=0;
@ -193,11 +193,8 @@ reg [128:0] instruction_count_temp;
finish<=2'd1; finish<=2'd1;
end end
end end
`endif
always @(negedge clock)begin
always @(negedge clock)begin
if(reset==1) if(reset==1)
cycles<=cycles+1; cycles<=cycles+1;
else begin else begin
@ -206,7 +203,9 @@ always @(negedge clock)begin
instruction_count <= 0; instruction_count <= 0;
`endif `endif
end end
end end
`endif
endmodule endmodule