Improved ALU and added more INC and a DEC instruction
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be06244021
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85bf886223
19
cpu/alu.v
19
cpu/alu.v
@ -1,9 +1,16 @@
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module ADDER16(input [15:0]A,input [15:0]B, input oe,output [15:0]OUT, output carry);
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wire c;
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wire [15:0]sum;
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assign {c,sum} = A+B;
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`include "alu_header.v"
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assign OUT = !oe ? sum : 16'hz;
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assign carry = !oe ? c : 'hz;
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module ALU(input [15:0]A,input [15:0]B, input oe,output reg [15:0]OUT,input [`ALU_OP_BITS-1:0]op);
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reg C_FLAG;
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always @ ( * ) begin
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case (op)
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`ALU_OP_ADD: {C_FLAG,OUT}=A+B;
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`ALU_OP_SUB: {C_FLAG,OUT}=A-B;
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`ALU_OP_AND: OUT=A&B;
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`ALU_OP_OR: OUT=A|B;
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`ALU_OP_XOR: OUT=A^B;
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endcase
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end
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endmodule
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6
cpu/alu_header.v
Normal file
6
cpu/alu_header.v
Normal file
@ -0,0 +1,6 @@
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`define ALU_OP_BITS 3
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`define ALU_OP_ADD 3'b000
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`define ALU_OP_SUB 3'b001
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`define ALU_OP_AND 3'b010
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`define ALU_OP_OR 3'b011
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`define ALU_OP_XOR 3'b100
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@ -4,5 +4,9 @@ MOV BX,#0x0000
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ADD AX,#0xDEAD
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ADD CX,#0xBEEF
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ADD CX,#0x4111
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mov AX,#0x00FF
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inc AL
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mov AX,#0x00FF
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inc ax
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ADD AX,#0x2200
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HLT
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@ -1,4 +1,5 @@
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`include "proc_state_def.v"
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`include "alu_header.v"
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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@ -39,7 +40,7 @@ always @(negedge reset) begin
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reg_write_we=1;
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reg_read_oe=1;
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unaligned_access=0;
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ALU_OUT=1;
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ALU_1OE=1;
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@(posedge reset)
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@(negedge clock);
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state=`PROC_IF_STATE_ENTRY;
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@ -60,11 +61,11 @@ register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_
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//ALU
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mux4 #(.WIDTH(16)) MUX16_1A(
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PARAM1,
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16'b0,
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reg_read_data,
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16'b0,
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16'b0,
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in1_sel,
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ADDER16_1A);
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ALU_1A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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PARAM2,
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@ -72,15 +73,15 @@ mux4 #(.WIDTH(16)) MUX16_1B(
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16'b0,
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16'b0,
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in2_sel,
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ADDER16_1B);
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ALU_1B);
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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reg ALU_OUT;
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reg [15:0] temp_out;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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wire [15:0] ALU_1A;
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wire [15:0] ALU_1B;
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wire [15:0] ALU_1O;
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reg [`ALU_OP_BITS-1:0]ALU_1OP;
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reg ALU_1OE;
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//reg [15:0] temp_out;
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ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP);
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/*** Processor stages ***/
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@ -99,8 +100,8 @@ always @(negedge clock) begin
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end
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end
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`PROC_IF_STATE_EXTRA_FETCH:begin
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CIR[7:0] <= external_data_bus[15:8];
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state=`PROC_DE_STATE_ENTRY;
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CIR[7:0] <= external_data_bus[15:8];
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state=`PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_EXIT:begin
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case(out_sel)
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@ -131,7 +132,7 @@ always @(posedge clock) begin
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write <= 1;
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reg_read_oe=1;
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reg_write_we=1;
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ALU_OUT=1;
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ALU_1OE=1;
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state=`PROC_IF_WRITE_CIR;
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end
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`PROC_IF_STATE_EXTRA_FETCH_SET:begin
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@ -154,7 +155,8 @@ always @(posedge clock) begin
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reg_read_addr={CIR[8:8],3'b000};
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reg_write_addr={CIR[8:8],3'b000};
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reg_read_oe=0;
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ALU_OUT=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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else begin
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@ -179,7 +181,8 @@ always @(posedge clock) begin
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reg_read_addr={CIR[8:8],CIR[2:0]};
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reg_write_addr={CIR[8:8],CIR[2:0]};
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reg_read_oe=0;
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ALU_OUT=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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state=`PROC_DE_LOAD_16_PARAM;
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if(CIR[8:8]==1)
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state=`PROC_DE_LOAD_16_PARAM;
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@ -206,7 +209,8 @@ always @(posedge clock) begin
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reg_write_addr={1'b0,CIR[10:8]};
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PARAM1[7:0]=CIR[7:0];
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PARAM2=0;
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ALU_OUT=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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state=`PROC_EX_STATE_ENTRY;
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end
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6'b101110,
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@ -217,10 +221,31 @@ always @(posedge clock) begin
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in2_sel=2'b00;
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out_sel=2'b11;
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reg_write_addr={1'b1,CIR[10:8]};
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ALU_OUT=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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PARAM2=0;
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state=`PROC_DE_LOAD_16_PARAM;
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end
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6'b010000,//INC
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6'b010001,//INC
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6'b010010,//DEC
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6'b010011:begin//DEC
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/*INC/DEC Register*/
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unaligned_access=~unaligned_access;
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in1_sel=2'b01;
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in2_sel=2'b00;
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out_sel=2'b11;
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PARAM2=1;
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reg_read_addr={1'b1,CIR[10:8]};
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reg_write_addr={1'b1,CIR[10:8]};
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reg_read_oe=0;
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ALU_1OE=0;
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if(CIR[11:11]==0)
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ALU_1OP=`ALU_OP_ADD;
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else
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ALU_1OP=`ALU_OP_SUB;
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state=`PROC_EX_STATE_ENTRY;
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end
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6'b111111 : begin
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/* INC */
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if (CIR[9:9] == 1 ) begin
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@ -238,7 +263,8 @@ always @(posedge clock) begin
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reg_read_addr={1'b0,CIR[2:0]};
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reg_write_addr={1'b0,CIR[2:0]};
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reg_read_oe=0;
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ALU_OUT=0;
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ALU_1OE=0;
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ALU_1OP=`ALU_OP_ADD;
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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@ -286,7 +312,7 @@ always @(posedge clock) begin
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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reg_write_data=ADDER16_1O;
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reg_write_data=ALU_1O;
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state=`PROC_EX_STATE_EXIT;
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ERROR=0;
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end
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