From 85bf8862238884cdf23dec1066288d4f08d417c3 Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Sat, 11 Feb 2023 14:43:53 +0000 Subject: [PATCH] Improved ALU and added more INC and a DEC instruction --- cpu/alu.v | 19 +++++++++----- cpu/alu_header.v | 6 +++++ cpu/boot_code.asm | 4 +++ cpu/processor.v | 66 +++++++++++++++++++++++++++++++++-------------- 4 files changed, 69 insertions(+), 26 deletions(-) create mode 100644 cpu/alu_header.v diff --git a/cpu/alu.v b/cpu/alu.v index 9d8043c..192f1c5 100644 --- a/cpu/alu.v +++ b/cpu/alu.v @@ -1,9 +1,16 @@ -module ADDER16(input [15:0]A,input [15:0]B, input oe,output [15:0]OUT, output carry); -wire c; -wire [15:0]sum; -assign {c,sum} = A+B; +`include "alu_header.v" -assign OUT = !oe ? sum : 16'hz; -assign carry = !oe ? c : 'hz; +module ALU(input [15:0]A,input [15:0]B, input oe,output reg [15:0]OUT,input [`ALU_OP_BITS-1:0]op); +reg C_FLAG; + +always @ ( * ) begin + case (op) + `ALU_OP_ADD: {C_FLAG,OUT}=A+B; + `ALU_OP_SUB: {C_FLAG,OUT}=A-B; + `ALU_OP_AND: OUT=A&B; + `ALU_OP_OR: OUT=A|B; + `ALU_OP_XOR: OUT=A^B; + endcase +end endmodule diff --git a/cpu/alu_header.v b/cpu/alu_header.v new file mode 100644 index 0000000..c914a4d --- /dev/null +++ b/cpu/alu_header.v @@ -0,0 +1,6 @@ +`define ALU_OP_BITS 3 +`define ALU_OP_ADD 3'b000 +`define ALU_OP_SUB 3'b001 +`define ALU_OP_AND 3'b010 +`define ALU_OP_OR 3'b011 +`define ALU_OP_XOR 3'b100 diff --git a/cpu/boot_code.asm b/cpu/boot_code.asm index b6a6d02..1f66123 100644 --- a/cpu/boot_code.asm +++ b/cpu/boot_code.asm @@ -4,5 +4,9 @@ MOV BX,#0x0000 ADD AX,#0xDEAD ADD CX,#0xBEEF ADD CX,#0x4111 +mov AX,#0x00FF +inc AL +mov AX,#0x00FF +inc ax ADD AX,#0x2200 HLT diff --git a/cpu/processor.v b/cpu/processor.v index 1805e6e..f8b8053 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -1,4 +1,5 @@ `include "proc_state_def.v" +`include "alu_header.v" module mux4 (in1,in2,in3,in4, sel,out); input [0:1] sel; @@ -39,7 +40,7 @@ always @(negedge reset) begin reg_write_we=1; reg_read_oe=1; unaligned_access=0; - ALU_OUT=1; + ALU_1OE=1; @(posedge reset) @(negedge clock); state=`PROC_IF_STATE_ENTRY; @@ -60,11 +61,11 @@ register_file register_file(reg_write_addr,reg_write_data,reg_write_we,reg_read_ //ALU mux4 #(.WIDTH(16)) MUX16_1A( PARAM1, - 16'b0, + reg_read_data, 16'b0, 16'b0, in1_sel, - ADDER16_1A); + ALU_1A); mux4 #(.WIDTH(16)) MUX16_1B( PARAM2, @@ -72,15 +73,15 @@ mux4 #(.WIDTH(16)) MUX16_1B( 16'b0, 16'b0, in2_sel, - ADDER16_1B); + ALU_1B); -wire [15:0] ADDER16_1A; -wire [15:0] ADDER16_1B; -wire [15:0] ADDER16_1O; -wire ADDER16_1C; -reg ALU_OUT; -reg [15:0] temp_out; -ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C); +wire [15:0] ALU_1A; +wire [15:0] ALU_1B; +wire [15:0] ALU_1O; +reg [`ALU_OP_BITS-1:0]ALU_1OP; +reg ALU_1OE; +//reg [15:0] temp_out; +ALU ALU(ALU_1A,ALU_1B,ALU_1OE,ALU_1O,ALU_1OP); /*** Processor stages ***/ @@ -99,8 +100,8 @@ always @(negedge clock) begin end end `PROC_IF_STATE_EXTRA_FETCH:begin - CIR[7:0] <= external_data_bus[15:8]; - state=`PROC_DE_STATE_ENTRY; + CIR[7:0] <= external_data_bus[15:8]; + state=`PROC_DE_STATE_ENTRY; end `PROC_EX_STATE_EXIT:begin case(out_sel) @@ -131,7 +132,7 @@ always @(posedge clock) begin write <= 1; reg_read_oe=1; reg_write_we=1; - ALU_OUT=1; + ALU_1OE=1; state=`PROC_IF_WRITE_CIR; end `PROC_IF_STATE_EXTRA_FETCH_SET:begin @@ -154,7 +155,8 @@ always @(posedge clock) begin reg_read_addr={CIR[8:8],3'b000}; reg_write_addr={CIR[8:8],3'b000}; reg_read_oe=0; - ALU_OUT=0; + ALU_1OE=0; + ALU_1OP=`ALU_OP_ADD; if(CIR[8:8]==1) state=`PROC_DE_LOAD_16_PARAM; else begin @@ -179,7 +181,8 @@ always @(posedge clock) begin reg_read_addr={CIR[8:8],CIR[2:0]}; reg_write_addr={CIR[8:8],CIR[2:0]}; reg_read_oe=0; - ALU_OUT=0; + ALU_1OE=0; + ALU_1OP=`ALU_OP_ADD; state=`PROC_DE_LOAD_16_PARAM; if(CIR[8:8]==1) state=`PROC_DE_LOAD_16_PARAM; @@ -206,7 +209,8 @@ always @(posedge clock) begin reg_write_addr={1'b0,CIR[10:8]}; PARAM1[7:0]=CIR[7:0]; PARAM2=0; - ALU_OUT=0; + ALU_1OE=0; + ALU_1OP=`ALU_OP_ADD; state=`PROC_EX_STATE_ENTRY; end 6'b101110, @@ -217,10 +221,31 @@ always @(posedge clock) begin in2_sel=2'b00; out_sel=2'b11; reg_write_addr={1'b1,CIR[10:8]}; - ALU_OUT=0; + ALU_1OE=0; + ALU_1OP=`ALU_OP_ADD; PARAM2=0; state=`PROC_DE_LOAD_16_PARAM; end + 6'b010000,//INC + 6'b010001,//INC + 6'b010010,//DEC + 6'b010011:begin//DEC + /*INC/DEC Register*/ + unaligned_access=~unaligned_access; + in1_sel=2'b01; + in2_sel=2'b00; + out_sel=2'b11; + PARAM2=1; + reg_read_addr={1'b1,CIR[10:8]}; + reg_write_addr={1'b1,CIR[10:8]}; + reg_read_oe=0; + ALU_1OE=0; + if(CIR[11:11]==0) + ALU_1OP=`ALU_OP_ADD; + else + ALU_1OP=`ALU_OP_SUB; + state=`PROC_EX_STATE_ENTRY; + end 6'b111111 : begin /* INC */ if (CIR[9:9] == 1 ) begin @@ -238,7 +263,8 @@ always @(posedge clock) begin reg_read_addr={1'b0,CIR[2:0]}; reg_write_addr={1'b0,CIR[2:0]}; reg_read_oe=0; - ALU_OUT=0; + ALU_1OE=0; + ALU_1OP=`ALU_OP_ADD; state=`PROC_EX_STATE_ENTRY; end default:begin @@ -286,7 +312,7 @@ always @(posedge clock) begin state=`PROC_EX_STATE_ENTRY; end `PROC_EX_STATE_ENTRY:begin - reg_write_data=ADDER16_1O; + reg_write_data=ALU_1O; state=`PROC_EX_STATE_EXIT; ERROR=0; end