Efthimis/9086
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases 1 Wiki Activity

Fixed race condition giving garbage data on debug register write prints and ordering of reg write and instr fetch debug prints

Browse Source
This commit is contained in:
(Tim) Efthimis Kritikos 2023-03-12 08:53:21 +00:00
parent 9230900b75
commit 82baacfd5b
2 changed files with 31 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
system/processor.v
View File

@ -209,6 +209,16 @@ always @(posedge clock) begin
`PROC_HALT_STATE:begin `PROC_HALT_STATE:begin
end end
`PROC_IF_STATE_ENTRY:begin `PROC_IF_STATE_ENTRY:begin
BHE <= 0;
external_address_bus <= {4'b0,ProgCount};
IOMEM <= 0;
read <= 0;
write <= 1;
reg_write_we <= 1;
state <= `PROC_IF_WRITE_CIR;
reg_write_in_sel <= 2'b00;
end
`PROC_IF_WRITE_CIR:begin
`ifdef DEBUG_PC_ADDRESS `ifdef DEBUG_PC_ADDRESS
/* Weird (possible bug) where even though the /* Weird (possible bug) where even though the
* testbench stop the clock after ERROR gets * testbench stop the clock after ERROR gets
@ -221,16 +231,6 @@ always @(posedge clock) begin
$display("Fetched instruction at %0x",ProgCount - 0); $display("Fetched instruction at %0x",ProgCount - 0);
end end
`endif `endif
BHE <= 0;
external_address_bus <= {4'b0,ProgCount};
IOMEM <= 0;
read <= 0;
write <= 1;
reg_write_we <= 1;
state <= `PROC_IF_WRITE_CIR;
reg_write_in_sel <= 2'b00;
end
`PROC_IF_WRITE_CIR:begin
/*I built the entire decode stage with CIR /*I built the entire decode stage with CIR
* being big endian so just convert it here*/ * being big endian so just convert it here*/

31
system/registers.v
View File

@ -61,28 +61,39 @@ always @(negedge write_port1_we) begin
registers[ {1'b0,write_port1_addr[1:0]} ][7:0] <= write_port1_data[7:0]; registers[ {1'b0,write_port1_addr[1:0]} ][7:0] <= write_port1_data[7:0];
end end
end end
`ifdef DEBUG_REG_WRITES `ifdef DEBUG_REG_WRITES
// Icarus verilog really doesn't like non-blocking assignments
// here
/* verilator lint_off BLKSEQ */
if(write_port1_addr[3:2]==2'b11)begin if(write_port1_addr[3:2]==2'b11)begin
case(write_port1_addr[1:0]) case(write_port1_addr[1:0])
2'b00: debug_name<="sp"; 2'b00: debug_name="sp";
2'b01: debug_name<="bp"; 2'b01: debug_name="bp";
2'b10: debug_name<="si"; 2'b10: debug_name="si";
2'b11: debug_name<="di"; 2'b11: debug_name="di";
endcase endcase
end else begin end else begin
case(write_port1_addr[1:0]) case(write_port1_addr[1:0])
2'b00: debug_name<="ax"; 2'b00: debug_name="ax";
2'b01: debug_name<="cx"; 2'b01: debug_name="cx";
2'b10: debug_name<="dx"; 2'b10: debug_name="dx";
2'b11: debug_name<="bx"; 2'b11: debug_name="bx";
endcase endcase
end end
/* verilator lint_on BLKSEQ */
`endif
end
`ifdef DEBUG_REG_WRITES
always @(posedge write_port1_we) begin
if ( debug_name != "" ) /*At the start this triggers for some reason */
if (write_Wbit)begin if (write_Wbit)begin
$display("register %%%s update to $0x%04x",debug_name,registers[write_port1_addr[2:0]]); $display("register %%%s update to $0x%04x",debug_name,registers[write_port1_addr[2:0]]);
end else begin end else begin
$display("register %%%s update to $0x%04x",debug_name,registers[{1'b0,write_port1_addr[1:0]}]); $display("register %%%s update to $0x%04x",debug_name,registers[{1'b0,write_port1_addr[1:0]}]);
end end
`endif
end end
`endif
endmodule endmodule