From 82baacfd5b33bd8c5573051eedceec2b4c7c843a Mon Sep 17 00:00:00 2001
From: "(Tim) Efthimis Kritikos" <efkf@firemail.cc>
Date: Sun, 12 Mar 2023 08:53:21 +0000
Subject: [PATCH] Fixed race condition giving garbage data on debug register
 write prints and ordering of reg write and instr fetch debug prints

---
 system/processor.v | 20 ++++++++++----------
 system/registers.v | 31 +++++++++++++++++++++----------
 2 files changed, 31 insertions(+), 20 deletions(-)

diff --git a/system/processor.v b/system/processor.v
index a0d8157..341f4e6 100644
--- a/system/processor.v
+++ b/system/processor.v
@@ -209,6 +209,16 @@ always @(posedge clock) begin
 		`PROC_HALT_STATE:begin
 		end
 		`PROC_IF_STATE_ENTRY:begin
+			BHE <= 0;
+			external_address_bus <= {4'b0,ProgCount};
+			IOMEM <= 0;
+			read <= 0;
+			write <= 1;
+			reg_write_we <= 1;
+			state <= `PROC_IF_WRITE_CIR;
+			reg_write_in_sel <= 2'b00;
+		end
+		`PROC_IF_WRITE_CIR:begin
 			`ifdef DEBUG_PC_ADDRESS
 				/* Weird (possible bug) where even though the
 				* testbench stop the clock after ERROR gets
@@ -221,16 +231,6 @@ always @(posedge clock) begin
 						$display("Fetched instruction at %0x",ProgCount - 0);
 				end
 			`endif
-			BHE <= 0;
-			external_address_bus <= {4'b0,ProgCount};
-			IOMEM <= 0;
-			read <= 0;
-			write <= 1;
-			reg_write_we <= 1;
-			state <= `PROC_IF_WRITE_CIR;
-			reg_write_in_sel <= 2'b00;
-		end
-		`PROC_IF_WRITE_CIR:begin
 			/*I built the entire decode stage with CIR
 			* being big endian so just convert it here*/
 
diff --git a/system/registers.v b/system/registers.v
index 4917af0..133ccaa 100644
--- a/system/registers.v
+++ b/system/registers.v
@@ -61,28 +61,39 @@ always @(negedge write_port1_we) begin
 			registers[ {1'b0,write_port1_addr[1:0]} ][7:0] <= write_port1_data[7:0];
 		end
 	end
-
 	`ifdef DEBUG_REG_WRITES
+		// Icarus verilog really doesn't like non-blocking assignments
+		// here
+		/* verilator lint_off BLKSEQ */
 		if(write_port1_addr[3:2]==2'b11)begin
 			case(write_port1_addr[1:0])
-				2'b00: debug_name<="sp";
-				2'b01: debug_name<="bp";
-				2'b10: debug_name<="si";
-				2'b11: debug_name<="di";
+				2'b00: debug_name="sp";
+				2'b01: debug_name="bp";
+				2'b10: debug_name="si";
+				2'b11: debug_name="di";
 			endcase
 		end else begin
 			case(write_port1_addr[1:0])
-				2'b00: debug_name<="ax";
-				2'b01: debug_name<="cx";
-				2'b10: debug_name<="dx";
-				2'b11: debug_name<="bx";
+				2'b00: debug_name="ax";
+				2'b01: debug_name="cx";
+				2'b10: debug_name="dx";
+				2'b11: debug_name="bx";
 			endcase
 		end
+		/* verilator lint_on BLKSEQ */
+	`endif
+
+end
+
+`ifdef DEBUG_REG_WRITES
+always @(posedge write_port1_we) begin
+	if ( debug_name != "" ) /*At the start this triggers for some reason */
 		if (write_Wbit)begin
 			$display("register %%%s update to $0x%04x",debug_name,registers[write_port1_addr[2:0]]);
 		end else begin
 			$display("register %%%s update to $0x%04x",debug_name,registers[{1'b0,write_port1_addr[1:0]}]);
 		end
-	`endif
 end
+`endif
+
 endmodule