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FPGA_Board/OrangeCrab_r0.2.1: Switched the GPIO 0/1 pins for I2C to the dedicated ones

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This commit is contained in:
(Tim) Efthimis Kritikos 2023-12-10 04:37:07 +00:00
parent 3e66336456
commit 8281c9a21f
2 changed files with 8 additions and 5 deletions
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8
system/fpga_config/OrangeCrab_r0.2.1/fpga_top.v
View File

@ -48,8 +48,8 @@ module fpga_top(
output wire [5:0] ddram_vccio, output wire [5:0] ddram_vccio,
output wire ddram_we_n, output wire ddram_we_n,
inout gpio_0,/*sda*/ inout i2c_sda,/*sda*/
output gpio_1 /*scl*/ output i2c_scl /*scl*/
`else `else
output i2c_dir, output i2c_dir,
output i2c_scl, output i2c_scl,
@ -493,7 +493,7 @@ TRELLIS_IO #(
.DIR ("BIDIR") .DIR ("BIDIR")
) TRELLIS_IO_00 ( ) TRELLIS_IO_00 (
// pin // pin
.B (gpio_0), .B (i2c_sda),
//input //input
.I (1'd0), .I (1'd0),
//Direction //Direction
@ -502,7 +502,7 @@ TRELLIS_IO #(
.O (SDA_input) .O (SDA_input)
); );
assign gpio_1=SCL; assign i2c_scl=SCL;
`else `else

5
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf
View File

@ -1,7 +1,6 @@
LOCATE COMP "clk48" SITE "A9"; LOCATE COMP "clk48" SITE "A9";
IOBUF PORT "clk48" IO_TYPE=LVCMOS33; IOBUF PORT "clk48" IO_TYPE=LVCMOS33;
FREQUENCY PORT "clk48" 48.0 MHz; FREQUENCY PORT "clk48" 48.0 MHz;
LOCATE COMP "ddram_a[0]" SITE "C4"; LOCATE COMP "ddram_a[0]" SITE "C4";
IOBUF PORT "ddram_a[0]" SLEWRATE=FAST; IOBUF PORT "ddram_a[0]" SLEWRATE=FAST;
IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I; IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I;
@ -252,3 +251,7 @@ LOCATE COMP "usb_d_n" SITE "M2";
IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33; IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
LOCATE COMP "usb_pullup" SITE "N2"; LOCATE COMP "usb_pullup" SITE "N2";
IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33; IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
LOCATE COMP "i2c_sda" SITE "C10";
IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33;
LOCATE COMP "i2c_scl" SITE "C9";
IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33;