518 lines
12 KiB
Verilog
518 lines
12 KiB
Verilog
/* top.v - Implements FPGA and Board specific circuitry
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This file is part of the 9086 project.
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Copyright (c) 2023 Efthymios Kritikos
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "error_header.v"
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`ifdef OUTPUT_JSON_STATISTICS
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`include "config.v"
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`endif
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module fpga_top(
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input clk48,
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input user_button,
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// output reset_n,
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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`ifdef SYNTHESIS
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output wire [15:0] ddram_a, // [15:13] are unused in litex as well, they just also route them through a trellis block
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output wire [2:0] ddram_ba,
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output wire ddram_cas_n,
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output wire ddram_cke,
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output wire ddram_clk_p,
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output wire ddram_cs_n,
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output wire [1:0] ddram_dm,
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input wire [15:0] ddram_dq,
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input wire [1:0] ddram_dqs_p,
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output wire [1:0] ddram_gnd,
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output wire ddram_odt,
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output wire ddram_ras_n,
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output wire ddram_reset_n,
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output wire [5:0] ddram_vccio,
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output wire ddram_we_n,
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inout i2c_sda,/*sda*/
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output i2c_scl /*scl*/
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`else
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output i2c_dir,
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output i2c_scl,
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input i2c_sda_in,
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output i2c_sda_out
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`endif
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);
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`ifndef SYNTHESIS
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string waveform_name;
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initial begin
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p,cycles);
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end
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end
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//TODO: should there be some common file between all the fpga_tops and system.v for this stuff?
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always @(posedge clk48) begin
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if(HALT==1&&disp_cache_start==disp_cache_end)begin
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$finish;
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end
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end
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reg sane;
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always @(posedge reset)begin sane<=1; end
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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end
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endcase
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$finish;
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end
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end
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`endif
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`ifdef SYNTHESIS
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assign ddram_a[15:13] = 3'b0;
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assign ddram_vccio = 6'd63;
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assign ddram_gnd = 2'd0;
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`endif
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wire HALT;
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wire [`ERROR_BITS-1:0]ERROR;
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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wire CPU_SPEED;
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processor p(
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.clock(CPU_SPEED),
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.reset(reset),
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.HALT(HALT),
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.ERROR(ERROR),
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.external_address_bus(address_bus),
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.external_data_bus_read(data_bus_read),
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.external_data_bus_write(data_bus_write),
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.wait_state(wait_state),
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.read(rd),
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.write(wr),
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.BHE(BHE),
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.IOMEM(IOMEM)
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,.new_instruction(new_instruction)
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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/* */ ,.L1_SIZE_STAT(L1_SIZE_STAT), .VALID_INSTRUCTION_STAT(VALID_INSTRUCTION_STAT), .jump_req_debug(jump_req_debug)
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`endif
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);
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/* verilator lint_off UNUSEDSIGNAL */
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`ifdef CALCULATE_IPC
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wire new_instruction;
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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wire [`L1_CACHE_SIZE-1:0]L1_SIZE_STAT;
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wire VALID_INSTRUCTION_STAT;
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wire jump_req_debug;
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`endif
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/* verilator lint_on UNUSEDSIGNAL */
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reg [2:0]rgb_led_color;
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assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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// A bit useless since if the cpu ERRORS out or HALTS it will continue executing anyway
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//always @(HALT or ERROR or user_button) begin
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// if (HALT==1) begin
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// /* yellow */
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// rgb_led_color<=3'b100;
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// end else if (ERROR != `ERROR_BITS'b0) begin
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// /* red */
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// rgb_led_color<=3'b110;
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// end else begin
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// /* green */
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// rgb_led_color<=3'b101;
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// end
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//end
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// Create a 27 bit register
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reg [26:0] counter = 0;
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// Every positive edge increment register by 1
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always @(posedge clk48) begin
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counter <= counter + 1;
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end
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/*** RESET CIRCUIT ***/
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reg reset=0;
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reg [1:0] state=0;
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always @(posedge counter[15]) begin
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if(user_button==0)
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state<=2'b00;
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case (state)
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2'b00:begin
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reset<=0;
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state<=2'b01;
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end
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2'b01:begin
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reset<=1;
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state<=2'b10;
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end
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default: begin
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end
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endcase
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end
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//------------------------------------------//
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// Cache to allow the slow display to have a
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// chance to keep up with the relentless CPU
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reg [6:0] disp_cache_start=0;
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reg [6:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [127:0];
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reg ascii_state=0;
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always @(posedge CPU_SPEED)begin
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if(wr==0)begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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disp_write_cache[disp_cache_end]<=data_bus_write[15:8];
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disp_cache_end<=disp_cache_end+7'd1;
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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rgb_led_color<=3'b000;
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else
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rgb_led_color<=3'b111;
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end
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end else if(ascii_state==1'b0)begin
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if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
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`ifndef SYNTHESIS
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$write("%s" ,disp_write_cache[disp_cache_start]); // TODO: maybe simulate the i2c lcd
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`endif
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ascii_data<=disp_write_cache[disp_cache_start];
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disp_cache_start<=disp_cache_start+7'd1;
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ascii_data_write_req<=1;
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ascii_state<=1'b1;
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end
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end
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if(ascii_state==1'b1)begin
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if(!ascii_data_ready)begin
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ascii_data_write_req<=0;
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ascii_state<=1'b0;
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end
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end
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end
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wire I2C_SPEED=counter[7];
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wire [15:0]boot_rom_data_bus_read;
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wire [15:0]boot_rom_data_bus_write;
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assign boot_rom_data_bus_write=data_bus_write;
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wire boot_rom_cs_n;
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doublemem #( .RAM_SIZE_IN_BYTES(2048) ) boot_rom
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( address_bus[10:0],boot_rom_data_bus_read,boot_rom_data_bus_write,rd,wr,BHE,boot_rom_cs_n,CPU_SPEED );
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/// Memory Map
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assign data_bus_read = ( IOMEM == 1 ) ? data_bus_read_IO : data_bus_read_MEM ;
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wire [15:0] data_bus_read_IO = ( address_bus[7:1] == 7'h10 ) ? LITEDRAM_STATUS_REGISTER : Wishbone_driver_data_bus_read;
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assign boot_rom_cs_n = !((IOMEM==0)&&(address_bus[15:12]==4'hF));
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wire [15:0] data_bus_read_MEM = (address_bus[15:12]==4'hF)?boot_rom_data_bus_read:data_bus_read_DDR3;
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wire DDR3_ram_cs = (IOMEM==0)&&(address_bus[15:12]!=4'hF);
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//
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// 0x20 | DDR STATUS BYTE1 |
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// 0x21 | DDR STATUS BYTE1 |
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// | |
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// - | -- |
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// | |
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// 0x30 | WISHBONE |
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// .. | .. |
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// 0x3F | WISHBONE |
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//
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assign wishbone_cs=!((IOMEM==1)&&(address_bus[7:4] == 4'h4));
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/// DDR3 Controller
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wire ddr3_init_done,ddr3_init_error,ddr3_pll_locked;
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/* verilator lint_off UNUSEDSIGNAL */
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wire user_rst;
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/* verilator lint_on UNUSEDSIGNAL */
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`ifndef SYNTHESIS
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assign ddr3_pll_locked=1;
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wire sim_trace;
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assign sim_trace=0;//signal is not connected on litedram, not sure what was the idea behind it
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`endif
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wire [15:0]Wishbone_driver_data_bus_read;
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wire [15:0]Wishbone_driver_data_bus_write=data_bus_write;
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wire wishbone_cs;
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Wishbone_IO_driver Wishbone_IO_driver(
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///// GENERAL //////
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.clock(CPU_SPEED),
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.reset_n(reset),
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////// CPU INTERFACE ///////
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.address(address_bus[3:1]),
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.data_bus_in(Wishbone_driver_data_bus_write),
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.data_bus_out(Wishbone_driver_data_bus_read),
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.read_n(rd),
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.write_n(wr),
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.chip_select_n(wishbone_cs),
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////// WISHBONE INTERFACE /////
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.wb_ctrl_ack(wb_ctrl_ack),
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.wb_ctrl_adr(wb_ctrl_adr),
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.wb_ctrl_cyc(wb_ctrl_cyc),
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.wb_ctrl_err(wb_ctrl_err),
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.wb_ctrl_sel(wb_ctrl_sel),
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.wb_ctrl_stb(wb_ctrl_stb),
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.wb_ctrl_we(wb_ctrl_we),
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.wb_ctrl_bte(wb_ctrl_bte),
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.wb_ctrl_cti(wb_ctrl_cti),
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.wb_ctrl_dat_r(wb_ctrl_dat_r),
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.wb_ctrl_dat_w(wb_ctrl_dat_w)
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);
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wire [15:0] LITEDRAM_STATUS_REGISTER = { 13'd0, ddr3_pll_locked ,ddr3_init_error, ddr3_init_done };
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wire [15:0] data_bus_read_DDR3;
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Wishbone_memory_driver Wishbone_memory_driver(
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///// GENERAL //////
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.clock(CPU_SPEED),
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.reset_n(reset),
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////// CPU INTERFACE ///////
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.address(address_bus),
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.BHE(BHE),
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.data_bus_in(data_bus_write),
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.data_bus_out(data_bus_read_DDR3),
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.wait_state(wait_state),
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.read_n(rd),
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.write_n(wr),
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.chip_select_n(!(DDR3_ram_cs&&ddr3_init_done)),
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////// WISHBONE INTERFACE /////
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.wb_mem_ack(wb_mem_ack),
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.wb_mem_adr(wb_mem_adr),
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.wb_mem_cyc(wb_mem_cyc),
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.wb_mem_err(wb_mem_err),
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.wb_mem_sel(wb_mem_sel),
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.wb_mem_stb(wb_mem_stb),
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.wb_mem_we(wb_mem_we),
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.wb_mem_data_r(wb_mem_data_r),
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.wb_mem_data_w(wb_mem_data_w)
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);
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wire wait_state;
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wire wb_ctrl_ack;
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wire [29:0] wb_ctrl_adr;
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wire [1:0] wb_ctrl_bte;
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wire [2:0] wb_ctrl_cti;
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wire wb_ctrl_cyc;
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wire [31:0] wb_ctrl_dat_r;
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wire [31:0] wb_ctrl_dat_w;
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wire wb_ctrl_err;
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wire [3:0] wb_ctrl_sel;
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wire wb_ctrl_stb;
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wire wb_ctrl_we;
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wire wb_mem_ack;
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wire [24:0] wb_mem_adr;
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wire wb_mem_cyc;
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wire [31:0] wb_mem_data_r;
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wire [31:0] wb_mem_data_w;
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wire wb_mem_err;
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wire [3:0] wb_mem_sel;
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wire wb_mem_stb;
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wire wb_mem_we;
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litedram_core DDR3_RAM_DRIVER(
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////// GENERAL ///////
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.clk(clk48),
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.user_clk(CPU_SPEED),
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`ifdef SYNTHESIS
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.rst(!reset),
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.pll_locked(ddr3_pll_locked),
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`else
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.sim_trace(sim_trace),
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`endif
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////// DDR3 INTERFACE //////
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`ifdef SYNTHESIS
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.ddram_a(ddram_a[12:0]), //also ignored on the litedram core
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.ddram_ba(ddram_ba),
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.ddram_cas_n(ddram_cas_n),
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.ddram_cke(ddram_cke),
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.ddram_clk_n(1'b0), // goes nowhere ...
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.ddram_clk_p(ddram_clk_p),
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.ddram_cs_n(ddram_cs_n),
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.ddram_dm(ddram_dm),
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.ddram_dq(ddram_dq),
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.ddram_dqs_n(2'b00), // goes nowhere ...
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.ddram_dqs_p(ddram_dqs_p),
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.ddram_odt(ddram_odt),
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.ddram_ras_n(ddram_ras_n),
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.ddram_reset_n(ddram_reset_n),
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.ddram_we_n(ddram_we_n),
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`endif
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/////// SYSTEM MEMORY INTERFACE ////////////////
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.init_done(ddr3_init_done),
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.init_error(ddr3_init_error),
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.user_port_wishbone_0_ack(wb_mem_ack),
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.user_port_wishbone_0_adr(wb_mem_adr),
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.user_port_wishbone_0_cyc(wb_mem_cyc),
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.user_port_wishbone_0_dat_r(wb_mem_data_r),
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.user_port_wishbone_0_dat_w(wb_mem_data_w),
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.user_port_wishbone_0_err(wb_mem_err),
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.user_port_wishbone_0_sel(wb_mem_sel),
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.user_port_wishbone_0_stb(wb_mem_stb),
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.user_port_wishbone_0_we(wb_mem_we),
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.user_rst(user_rst),
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/////// WISHBONE CONTROL INTERFACE ///////////
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.wb_ctrl_ack(wb_ctrl_ack),
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.wb_ctrl_adr(wb_ctrl_adr),
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.wb_ctrl_cyc(wb_ctrl_cyc),
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.wb_ctrl_err(wb_ctrl_err),
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.wb_ctrl_sel(wb_ctrl_sel),
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.wb_ctrl_stb(wb_ctrl_stb),
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.wb_ctrl_we(wb_ctrl_we),
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.wb_ctrl_bte(wb_ctrl_bte),
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.wb_ctrl_cti(wb_ctrl_cti),
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.wb_ctrl_dat_r(wb_ctrl_dat_r),
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.wb_ctrl_dat_w(wb_ctrl_dat_w)
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);
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// Display driver
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wire ascii_data_ready;
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reg ascii_data_write_req=0;
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reg [7:0] ascii_data;
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ascii_to_HD44780_driver LCD_DRIVER(
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/* system */
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I2C_SPEED,
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1'b1,
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/* Data Input */
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ascii_data_ready,
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ascii_data_write_req,
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ascii_data,
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/* write circuitry */
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!pcf_busy,
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pcf_write_req,
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pcf_data,
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pcf_command_data
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);
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// Port expander driver
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wire pcf_write_req,pcf_command_data,pcf_busy;
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wire [3:0]pcf_data;
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wire [7:0]i2c_data;
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pcf8574_for_HD44780 PCF8574_driver(
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.clock(I2C_SPEED),
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.pcf_write_req(pcf_write_req),
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.pcf_command_data(pcf_command_data),
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.pcf_data(pcf_data),
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.pcf_busy(pcf_busy),
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.new_backlight(1'b0),
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.backlight_update(1'b0),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data)
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);
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// I2C driver
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wire SDA_direction;
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wire SCL,SDA_input,SDA_output,I2C_BUSY,I2C_SEND;
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I2C_driver i2c_driver(
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.clock(I2C_SPEED),
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.SDA_input(SDA_input),
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.SDA_output(SDA_output),
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.SDA_direction(SDA_direction),
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.SCL(SCL),
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.address(7'h27),
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.I2C_BUSY(I2C_BUSY),
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.I2C_SEND(I2C_SEND),
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.i2c_data(i2c_data)
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);
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`ifdef SYNTHESIS
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TRELLIS_IO #(
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// Parameters.
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|
.DIR ("BIDIR")
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|
) TRELLIS_IO_00 (
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// pin
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|
.B (i2c_sda),
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|
//input
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|
.I (1'd0),
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|
//Direction
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|
.T (~( SDA_direction & (~SDA_output) )),
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// Output
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|
.O (SDA_input)
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|
);
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assign i2c_scl=SCL;
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`else
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assign i2c_dir=SDA_direction;
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assign i2c_scl=SCL;
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assign SDA_input=i2c_sda_in;
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assign i2c_sda_out=SDA_output;
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`endif
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|
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endmodule
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