Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!

This commit is contained in:
(Tim) Efthimis Kritikos 2023-05-17 21:28:50 +01:00
parent 90f63b525d
commit 7db70d79ff
4 changed files with 24 additions and 46 deletions

View File

@ -107,7 +107,7 @@ wire [`UCODE_DATA_BITS-1:0] ucode_data;
microcode ucode(seq_addr_input,ucode_data); microcode ucode(seq_addr_input,ucode_data);
`define invalid_instruction next_state=`EXEC_DONE;ERROR<=`ERR_UNIMPL_INSTRUCTION;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION; `define invalid_instruction next_state=`EXEC_WAIT;ERROR<=`ERR_UNIMPL_INSTRUCTION;IN_MOD=3'b011;seq_addr_entry<=`UCODE_NO_INSTRUCTION;
//TODO: A possible optimisation for instruction with 8bit parameter and //TODO: A possible optimisation for instruction with 8bit parameter and
@ -362,7 +362,7 @@ always @( FLAGS or CIR or SIMPLE_MICRO or seq_addr_input ) begin
ERROR<=`ERR_NO_ERROR; ERROR<=`ERR_NO_ERROR;
MEM_OR_IO=0; MEM_OR_IO=0;
seq_addr_entry<=`UCODE_NO_INSTRUCTION; seq_addr_entry<=`UCODE_NO_INSTRUCTION;
next_state=`EXEC_HALT; next_state=`EXEC_WAIT;
DEPENDS_ON_PREVIOUS<=0; DEPENDS_ON_PREVIOUS<=0;
memio_address_select=0; memio_address_select=0;
end end

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@ -21,9 +21,7 @@
`define EXEC_STATE_BITS 4 `define EXEC_STATE_BITS 4
`define EXEC_HALT 4'b0000 `define EXEC_WAIT 4'b1100
`define EXEC_DONE 4'b1100
/*DECODE SATE*/ /*DECODE SATE*/
`define EXEC_DE_LOAD_16_PARAM 4'b0010 `define EXEC_DE_LOAD_16_PARAM 4'b0010

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@ -69,14 +69,12 @@ ALU ALU1(
/*############ Execute logic ########################################################## */ /*############ Execute logic ########################################################## */
always @(posedge valid_input) begin always @(valid_input) begin
if(exec_state == `EXEC_DONE) begin
exec_state <= init_state; exec_state <= init_state;
reg_write_we <= 1; reg_write_we <= 1;
biu_jump_req <= 0; biu_jump_req <= 0;
use_exec_reg_addr <= 0; use_exec_reg_addr <= 0;
end end
end
always @( set_initial_values) begin always @( set_initial_values) begin
PARAM1 <= PARAM1_INIT; PARAM1 <= PARAM1_INIT;
@ -84,14 +82,16 @@ always @( set_initial_values) begin
end end
always @(negedge reset) begin always @(negedge reset) begin
exec_state <= `EXEC_HALT; exec_state <= `EXEC_WAIT;
end end
always @(posedge reset) begin always @(posedge reset) begin
exec_state <= `EXEC_RESET; exec_state <= `EXEC_RESET;
end end
`define unimpl_addressing_mode exec_state <= `EXEC_DONE;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE; `define unimpl_addressing_mode exec_state <= `EXEC_WAIT;ERROR <= `ERR_UNIMPL_ADDRESSING_MODE;
`define finished_instruction next_exec<=!next_exec; exec_state <= `EXEC_WAIT;
always @(posedge clock) begin always @(posedge clock) begin
case (exec_state) case (exec_state)
@ -101,16 +101,13 @@ always @(posedge clock) begin
biu_data_direction <= 0; biu_data_direction <= 0;
biu_jump_req <= 0; biu_jump_req <= 0;
reg_write_we <= 1; reg_write_we <= 1;
exec_state <= `EXEC_DONE; exec_state <= `EXEC_WAIT;
next_exec <= 0; next_exec <= 0;
ERROR <= `ERR_NO_ERROR; ERROR <= `ERR_NO_ERROR;
end end
`EXEC_DONE:begin `EXEC_WAIT:begin
reg_write_we <= 1; reg_write_we <= 1;
use_exec_reg_addr <= 0; use_exec_reg_addr <= 0;
if(valid_input)begin
exec_state <= init_state;
end
end end
`EXEC_DE_LOAD_REG_TO_PARAM:begin `EXEC_DE_LOAD_REG_TO_PARAM:begin
PARAM2<=reg_read_port2_data; PARAM2<=reg_read_port2_data;
@ -235,9 +232,8 @@ always @(posedge clock) begin
end end
end end
`EXEC_NEXT_INSTRUCTION:begin `EXEC_NEXT_INSTRUCTION:begin
next_exec <= !next_exec; `finished_instruction
/*necessary for biu to see we went on another state from decode to give us a new instruction*/ /*necessary for biu to see we went on another state from decode to give us a new instruction*/
exec_state <= `EXEC_DONE;
end end
`EXEC_WRITE_ENTRY:begin `EXEC_WRITE_ENTRY:begin
FLAGS[7:0] <= ALU_FLAGS[7:0]; FLAGS[7:0] <= ALU_FLAGS[7:0];
@ -291,12 +287,10 @@ always @(posedge clock) begin
end end
3'b011:begin 3'b011:begin
reg_write_we <= 0; reg_write_we <= 0;
exec_state <= `EXEC_DONE; `finished_instruction
next_exec <= !next_exec;
end end
3'b100:begin /*No output*/ 3'b100:begin /*No output*/
exec_state <= `EXEC_DONE; `finished_instruction
next_exec <= !next_exec;
end end
3'b101:begin /* Program Counter*/ 3'b101:begin /* Program Counter*/
BIU_ADDRESS_INPUT <= ALU_O[15:0]; BIU_ADDRESS_INPUT <= ALU_O[15:0];
@ -310,8 +304,7 @@ always @(posedge clock) begin
end end
3'b111:begin /* Write to PRAM1 (for microcode calculations) */ 3'b111:begin /* Write to PRAM1 (for microcode calculations) */
PARAM1 <= ALU_O; PARAM1 <= ALU_O;
exec_state <= `EXEC_DONE; `finished_instruction
next_exec <= !next_exec;
end end
default:begin default:begin
`unimpl_addressing_mode `unimpl_addressing_mode
@ -320,8 +313,7 @@ always @(posedge clock) begin
end end
`EXEC_JUMP_RELEASE:begin `EXEC_JUMP_RELEASE:begin
biu_jump_req <= 0; biu_jump_req <= 0;
exec_state <= `EXEC_DONE; `finished_instruction
next_exec <= !next_exec;
end end
`EXEC_MEMIO_WRITE:begin `EXEC_MEMIO_WRITE:begin
/* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */ /* if memio_address_select == 0 ADDRESS: reg_read_port1_data DATA:ALU1_O */
@ -336,12 +328,9 @@ always @(posedge clock) begin
if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow if (write == 0) begin //TODO: don't do it that was or better yet don't do it at all somehow
biu_write_request <= 0; biu_write_request <= 0;
exec_state <= `EXEC_DONE; `finished_instruction
next_exec <= !next_exec;
end end
end
`EXEC_HALT:begin
end end
default:begin default:begin
end end

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@ -227,10 +227,9 @@ always @(next_exec) begin
ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end}; ProgCount <= INSTRUCTION_LOCATION+{12'b0,instr_end};
INSTRUCTION_BUFFER<=INSTRUCTION[23:0]; INSTRUCTION_BUFFER<=INSTRUCTION[23:0];
wait_exec<=1; wait_exec<=1;
valid_exec_data<=1; valid_exec_data<=!valid_exec_data;
end else begin end else begin
wait_exec<=0; wait_exec<=0;
valid_exec_data<=0;
end end
end end
@ -246,6 +245,7 @@ always @(posedge clock) begin
owe_set_init <= 0; owe_set_init <= 0;
set_initial_values<=0; set_initial_values<=0;
wait_exec<=0; wait_exec<=0;
valid_exec_data<=0;
end end
`PROC_DE_STATE_ENTRY:begin `PROC_DE_STATE_ENTRY:begin
if( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin if( VALID_INSTRUCTION==1 || SIMPLE_MICRO == 1 ) begin
@ -274,7 +274,7 @@ always @(posedge clock) begin
/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/ /*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
end else begin end else begin
/* This runs at the start of each execution cycle, with microcode this is more than once per 8086 instruction */ /* This runs at the start of each execution cycle, with microcode this is more than once per 8086 instruction */
valid_exec_data <= 1; valid_exec_data<=!valid_exec_data;
if( SIMPLE_MICRO == 1 ) begin if( SIMPLE_MICRO == 1 ) begin
ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/ ucode_seq_addr <= ucode_seq_addr_entry; /*Reused for next address*/
if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin if( ucode_seq_addr_entry == `UCODE_NO_INSTRUCTION )begin
@ -284,15 +284,6 @@ always @(posedge clock) begin
end end
wait_exec<=1; wait_exec<=1;
end end
end else begin
if( DE_DEPENDS_ON_PREVIOUS == 0 )
if ( (ucode_seq_addr==`UCODE_NO_INSTRUCTION) && (ucode_seq_addr_entry!=`UCODE_NO_INSTRUCTION) && valid_exec_data==0 )begin
/*switch to microcode decoding*/
ucode_seq_addr <= ucode_seq_addr_entry;
SIMPLE_MICRO <= 1;
owe_set_init <= 1;
/*keep proc_state the same and rerun decode this time with all the data from the microcode rom*/
end
end end
end end
end end
@ -304,7 +295,7 @@ always @(posedge clock) begin
end end
always @(exec_state) begin always @(exec_state) begin
if(exec_state == `EXEC_DONE) if(exec_state == `EXEC_WAIT)
FLAGS <= {8'b0,EXEC_FLAGS}; //TODO: don't set all of them all the time! FLAGS <= {8'b0,EXEC_FLAGS}; //TODO: don't set all of them all the time!
end end