Improved execution state logic, cleaned up code and fixed register file output enable
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a5571fda12
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185efe9d85
@ -1,18 +1,17 @@
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Thu Feb 9 20:13:04 2023
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[*] Fri Feb 10 01:43:01 2023
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[*]
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[dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2"
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[dumpfile_mtime] "Thu Feb 9 20:10:34 2023"
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[dumpfile_size] 1043
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[dumpfile_mtime] "Fri Feb 10 01:42:12 2023"
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[dumpfile_size] 1058
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[savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw"
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[timestart] 0
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[size] 1438 1059
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[pos] -1 -1
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*-22.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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*-21.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] tb.
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[treeopen] tb.p.
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[treeopen] tb.p.exec_units.
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[sst_width] 221
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[signals_width] 293
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[sst_expanded] 1
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@ -27,30 +26,11 @@ tb.p.external_data_bus[15:0]
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tb.p.CIR[15:0]
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@28
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tb.p.EXCEPTION[0]
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@c00022
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tb.p.exec_units.ADDER16_1.A[15:0]
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@28
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(0)tb.p.exec_units.ADDER16_1.A[15:0]
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(1)tb.p.exec_units.ADDER16_1.A[15:0]
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(2)tb.p.exec_units.ADDER16_1.A[15:0]
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(3)tb.p.exec_units.ADDER16_1.A[15:0]
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(4)tb.p.exec_units.ADDER16_1.A[15:0]
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(5)tb.p.exec_units.ADDER16_1.A[15:0]
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(6)tb.p.exec_units.ADDER16_1.A[15:0]
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(7)tb.p.exec_units.ADDER16_1.A[15:0]
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(8)tb.p.exec_units.ADDER16_1.A[15:0]
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(9)tb.p.exec_units.ADDER16_1.A[15:0]
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(10)tb.p.exec_units.ADDER16_1.A[15:0]
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(11)tb.p.exec_units.ADDER16_1.A[15:0]
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(12)tb.p.exec_units.ADDER16_1.A[15:0]
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(13)tb.p.exec_units.ADDER16_1.A[15:0]
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(14)tb.p.exec_units.ADDER16_1.A[15:0]
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(15)tb.p.exec_units.ADDER16_1.A[15:0]
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@1401200
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-group_end
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@22
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tb.p.exec_units.ADDER16_1.B[15:0]
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tb.p.ADDER16_1.A[15:0]
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tb.p.ADDER16_1.B[15:0]
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tb.p.ADDER16_1.OUT[15:0]
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@29
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tb.p.exec_units.register_file.write1[0]
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tb.p.reg_write[0]
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[pattern_trace] 1
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[pattern_trace] 0
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125
cpu/processor.v
125
cpu/processor.v
@ -1,63 +1,44 @@
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`include "proc_state_def.v"
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module exec_units ( input [15:0]PARAM1, input [15:0]PARAM2, input [1:0]in1_sel, input [1:0]in2_sel, input [1:0]out_sel , input EXEC);
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/*Architectural Register file*/
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wire [2:0] reg_addr;
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wire [15:0] reg_data;
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wire reg_read;
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wire reg_write;
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wire [2:0] reg_read_addr;
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wire [15:0] reg_read_data;
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wire reg_read_read;
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register_file register_file(reg_addr,reg_data,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);
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/*Exec Unts*/
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,EXEC,ADDER16_1O,ADDER16_1C);
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/*logic*/
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assign reg_addr=PARAM2[5:3];
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assign reg_read=EXEC;
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assign reg_write=EXEC;
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assign reg_read_read=0;
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assign reg_read_addr=PARAM2[2:0];
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assign ADDER16_1A= (in1_sel==2'b00) ? PARAM1 : 16'b1010101010101010;
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assign ADDER16_1B= (in2_sel==2'b01) ? reg_read_data : 16'b1010101010101010;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : 'hz;
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//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : ADDER16_1O;
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assign reg_data = ADDER16_1O;
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module mux4 (in1,in2,in3,in4, sel,out);
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input [0:1] sel;
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parameter WIDTH=16;
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input [WIDTH-1:0] in1,in2,in3,in4;
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output [WIDTH-1:0] out;
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assign out = (sel == 'b00) ? in1 :
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(sel == 'b01) ? in2 :
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(sel == 'b10) ? in3 :
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in4;
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endmodule
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module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT);
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/* State */
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/*** Global Definitions ***/
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// State
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reg [3:0] state;
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reg instruction_finished;
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/* Registers */
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// Registers
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reg [19:0] ProgCount;
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reg [15:0] CIR;
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reg [15:0] PARAM1;
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reg [15:0] PARAM2;
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/* Execution units*/
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// Execution units
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reg [1:0] in1_sel;
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reg [1:0] in2_sel;
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reg [1:0] out_sel;
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reg exec_unit_execute;
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exec_units exec_units(PARAM1,PARAM2,in1_sel,in2_sel,out_sel,exec_unit_execute);
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/* RESET LOGIC */
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/*** RESET LOGIC ***/
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always @(negedge reset) begin
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if (reset==0) begin
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@(posedge clock);
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ProgCount=0;//TODO: Reset Vector
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EXCEPTION=0;
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HALT=0;
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exec_unit_execute=1;
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reg_read=1;
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reg_write=1;
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reg_read_read=1;
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ALU_OUT=1;
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@(negedge clock);
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@(posedge clock);
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state=`PROC_IF_STATE_ENTRY;
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@ -66,7 +47,46 @@ end
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reg EXCEPTION;
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/* Processor stages */
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/*** ALU and EXEC stage logic ***/
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//Architectural Register file
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reg [2:0] reg_addr;
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reg [15:0] reg_data;
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reg reg_read;
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reg reg_write;
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reg [2:0] reg_read_addr;
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reg [15:0] reg_read_data;
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reg reg_read_read;
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wire [15:0] reg_data_;
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assign reg_data_=reg_data;
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register_file register_file(reg_addr,reg_data_,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read);
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//ALU
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mux4 #(.WIDTH(16)) MUX16_1A(
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PARAM1,
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16'b0,
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16'b0,
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16'b0,
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in1_sel,
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ADDER16_1A);
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mux4 #(.WIDTH(16)) MUX16_1B(
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16'b0,
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reg_read_data,
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16'b0,
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16'b0,
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in2_sel,
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ADDER16_1B);
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wire [15:0] ADDER16_1A;
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wire [15:0] ADDER16_1B;
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wire [15:0] ADDER16_1O;
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wire ADDER16_1C;
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reg ALU_OUT;
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reg [15:0] temp_out;
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ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C);
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/*** Processor stages ***/
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always @(negedge clock) begin
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case(state)
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`PROC_IF_WRITE_CIR:begin
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@ -75,7 +95,13 @@ always @(negedge clock) begin
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state=`PROC_DE_STATE_ENTRY;
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end
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`PROC_EX_STATE_EXIT:begin
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exec_unit_execute=1;
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case(out_sel)
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2'b01:begin
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reg_write=0;
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end
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default:begin
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end
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endcase
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state=`PROC_IF_STATE_ENTRY;
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end
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endcase
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@ -92,6 +118,9 @@ always @(posedge clock) begin
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external_address_bus <= ProgCount;
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read <= 0;
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write <= 1;
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reg_read_read=1;
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reg_write=1;
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ALU_OUT=1;
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state=`PROC_IF_WRITE_CIR;
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end
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`PROC_DE_STATE_ENTRY:begin
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@ -105,8 +134,10 @@ always @(posedge clock) begin
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in1_sel=2'b00;
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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reg_read_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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reg_read_read=0;
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ALU_OUT=0;
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state=`PROC_DE_LOAD_16_PARAM;
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end
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default:begin
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@ -124,8 +155,10 @@ always @(posedge clock) begin
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in2_sel=2'b01;
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out_sel=2'b01;
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PARAM1=1;
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PARAM2[2:0]=CIR[2:0];
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PARAM2[5:3]=CIR[2:0];
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reg_read_addr=CIR[2:0];
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reg_addr=CIR[2:0];
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reg_read_read=0;
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ALU_OUT=0;
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state=`PROC_EX_STATE_ENTRY;
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end
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default:begin
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@ -147,11 +180,13 @@ always @(posedge clock) begin
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state=`PROC_EX_STATE_ENTRY;
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end
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`PROC_EX_STATE_ENTRY:begin
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EXCEPTION=0;
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exec_unit_execute=0;
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reg_data=ADDER16_1O;
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state=`PROC_EX_STATE_EXIT;
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EXCEPTION=0;
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end
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endcase
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end
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endmodule
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@ -1,6 +1,6 @@
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module register_file ( input [2:0]addr1, inout [15:0]data1, input wire read1, input wire write1 ,input [2:0]addr2,output [15:0]data2,input wire read2);
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reg [15:0] registers [7:0];
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assign data2 = !read2 ? registers[0] : 'b1111000011110000 ;
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assign data2 = !read2 ? registers[0] : 'hz ;
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//assign data2 = !read2 ? registers[addr2]: 'b1111000011110000;
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assign data1 = !read1 ? registers[addr1]: 'hz;
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initial begin
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