22 lines
835 B
Verilog
22 lines
835 B
Verilog
module register_file ( input [2:0]addr1, inout [15:0]data1, input wire read1, input wire write1 ,input [2:0]addr2,output [15:0]data2,input wire read2);
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reg [15:0] registers [7:0];
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assign data2 = !read2 ? registers[0] : 'hz ;
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//assign data2 = !read2 ? registers[addr2]: 'b1111000011110000;
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assign data1 = !read1 ? registers[addr1]: 'hz;
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initial begin
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registers['b000]=0;
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registers['b001]=0;
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registers['b010]=0;
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registers['b011]=0;
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registers['b100]=0;
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registers['b101]=0;
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registers['b110]=0;
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registers['b111]=0; // TODO Don't clear. Remove after we implement the MOV instruction
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end
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always @(negedge write1) begin
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registers[addr1] = data1;
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//$display("registers: 0:%04x 1:%04x 2:%04x",registers[0],registers[1],registers[2]);
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$display("register %d update to %04x (data bus %04x)",addr1,registers[addr1],data1);
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end
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endmodule
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