From 185efe9d85b3fa4bd874b23fdb4fdb385b3c5c1c Mon Sep 17 00:00:00 2001 From: "(Tim) Efthimis Kritikos" Date: Fri, 10 Feb 2023 01:45:27 +0000 Subject: [PATCH] Improved execution state logic, cleaned up code and fixed register file output enable --- cpu/gtkwave_savefile.gtkw | 36 +++-------- cpu/processor.v | 125 ++++++++++++++++++++++++-------------- cpu/registers.v | 2 +- 3 files changed, 89 insertions(+), 74 deletions(-) diff --git a/cpu/gtkwave_savefile.gtkw b/cpu/gtkwave_savefile.gtkw index bcc765e..121166e 100644 --- a/cpu/gtkwave_savefile.gtkw +++ b/cpu/gtkwave_savefile.gtkw @@ -1,18 +1,17 @@ [*] [*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI -[*] Thu Feb 9 20:13:04 2023 +[*] Fri Feb 10 01:43:01 2023 [*] [dumpfile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/test.lx2" -[dumpfile_mtime] "Thu Feb 9 20:10:34 2023" -[dumpfile_size] 1043 +[dumpfile_mtime] "Fri Feb 10 01:42:12 2023" +[dumpfile_size] 1058 [savefile] "/home/user/UNI_DATA/COMS30046_2022_TB-2/projects/9086/cpu/gtkwave_savefile.gtkw" [timestart] 0 [size] 1438 1059 [pos] -1 -1 -*-22.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +*-21.795050 6163000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 [treeopen] tb. [treeopen] tb.p. -[treeopen] tb.p.exec_units. [sst_width] 221 [signals_width] 293 [sst_expanded] 1 @@ -27,30 +26,11 @@ tb.p.external_data_bus[15:0] tb.p.CIR[15:0] @28 tb.p.EXCEPTION[0] -@c00022 -tb.p.exec_units.ADDER16_1.A[15:0] -@28 -(0)tb.p.exec_units.ADDER16_1.A[15:0] -(1)tb.p.exec_units.ADDER16_1.A[15:0] -(2)tb.p.exec_units.ADDER16_1.A[15:0] -(3)tb.p.exec_units.ADDER16_1.A[15:0] -(4)tb.p.exec_units.ADDER16_1.A[15:0] -(5)tb.p.exec_units.ADDER16_1.A[15:0] -(6)tb.p.exec_units.ADDER16_1.A[15:0] -(7)tb.p.exec_units.ADDER16_1.A[15:0] -(8)tb.p.exec_units.ADDER16_1.A[15:0] -(9)tb.p.exec_units.ADDER16_1.A[15:0] -(10)tb.p.exec_units.ADDER16_1.A[15:0] -(11)tb.p.exec_units.ADDER16_1.A[15:0] -(12)tb.p.exec_units.ADDER16_1.A[15:0] -(13)tb.p.exec_units.ADDER16_1.A[15:0] -(14)tb.p.exec_units.ADDER16_1.A[15:0] -(15)tb.p.exec_units.ADDER16_1.A[15:0] -@1401200 --group_end @22 -tb.p.exec_units.ADDER16_1.B[15:0] +tb.p.ADDER16_1.A[15:0] +tb.p.ADDER16_1.B[15:0] +tb.p.ADDER16_1.OUT[15:0] @29 -tb.p.exec_units.register_file.write1[0] +tb.p.reg_write[0] [pattern_trace] 1 [pattern_trace] 0 diff --git a/cpu/processor.v b/cpu/processor.v index fe369bb..93d3707 100644 --- a/cpu/processor.v +++ b/cpu/processor.v @@ -1,63 +1,44 @@ `include "proc_state_def.v" -module exec_units ( input [15:0]PARAM1, input [15:0]PARAM2, input [1:0]in1_sel, input [1:0]in2_sel, input [1:0]out_sel , input EXEC); -/*Architectural Register file*/ -wire [2:0] reg_addr; -wire [15:0] reg_data; -wire reg_read; -wire reg_write; -wire [2:0] reg_read_addr; -wire [15:0] reg_read_data; -wire reg_read_read; -register_file register_file(reg_addr,reg_data,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read); - -/*Exec Unts*/ -wire [15:0] ADDER16_1A; -wire [15:0] ADDER16_1B; -wire [15:0] ADDER16_1O; -wire ADDER16_1C; -ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,EXEC,ADDER16_1O,ADDER16_1C); - -/*logic*/ -assign reg_addr=PARAM2[5:3]; -assign reg_read=EXEC; -assign reg_write=EXEC; -assign reg_read_read=0; -assign reg_read_addr=PARAM2[2:0]; -assign ADDER16_1A= (in1_sel==2'b00) ? PARAM1 : 16'b1010101010101010; -assign ADDER16_1B= (in2_sel==2'b01) ? reg_read_data : 16'b1010101010101010; -//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : 'hz; -//assign reg_data = (out_sel==2'b01) ? ADDER16_1O : ADDER16_1O; -assign reg_data = ADDER16_1O; +module mux4 (in1,in2,in3,in4, sel,out); +input [0:1] sel; +parameter WIDTH=16; +input [WIDTH-1:0] in1,in2,in3,in4; +output [WIDTH-1:0] out; +assign out = (sel == 'b00) ? in1 : + (sel == 'b01) ? in2 : + (sel == 'b10) ? in3 : + in4; endmodule module processor ( input clock, input reset , output reg [19:0] external_address_bus, inout [15:0] external_data_bus,output reg read, output reg write, output reg HALT); -/* State */ +/*** Global Definitions ***/ +// State reg [3:0] state; -reg instruction_finished; -/* Registers */ +// Registers reg [19:0] ProgCount; reg [15:0] CIR; reg [15:0] PARAM1; reg [15:0] PARAM2; -/* Execution units*/ +// Execution units reg [1:0] in1_sel; reg [1:0] in2_sel; reg [1:0] out_sel; -reg exec_unit_execute; -exec_units exec_units(PARAM1,PARAM2,in1_sel,in2_sel,out_sel,exec_unit_execute); -/* RESET LOGIC */ +/*** RESET LOGIC ***/ always @(negedge reset) begin if (reset==0) begin @(posedge clock); ProgCount=0;//TODO: Reset Vector EXCEPTION=0; HALT=0; - exec_unit_execute=1; + reg_read=1; + reg_write=1; + reg_read_read=1; + ALU_OUT=1; @(negedge clock); @(posedge clock); state=`PROC_IF_STATE_ENTRY; @@ -66,7 +47,46 @@ end reg EXCEPTION; -/* Processor stages */ +/*** ALU and EXEC stage logic ***/ + +//Architectural Register file +reg [2:0] reg_addr; +reg [15:0] reg_data; +reg reg_read; +reg reg_write; +reg [2:0] reg_read_addr; +reg [15:0] reg_read_data; +reg reg_read_read; +wire [15:0] reg_data_; +assign reg_data_=reg_data; +register_file register_file(reg_addr,reg_data_,reg_read,reg_write,reg_read_addr,reg_read_data,reg_read_read); + +//ALU +mux4 #(.WIDTH(16)) MUX16_1A( + PARAM1, + 16'b0, + 16'b0, + 16'b0, + in1_sel, + ADDER16_1A); + +mux4 #(.WIDTH(16)) MUX16_1B( + 16'b0, + reg_read_data, + 16'b0, + 16'b0, + in2_sel, + ADDER16_1B); + +wire [15:0] ADDER16_1A; +wire [15:0] ADDER16_1B; +wire [15:0] ADDER16_1O; +wire ADDER16_1C; +reg ALU_OUT; +reg [15:0] temp_out; +ADDER16 ADDER16_1(ADDER16_1A,ADDER16_1B,ALU_OUT,ADDER16_1O,ADDER16_1C); + +/*** Processor stages ***/ always @(negedge clock) begin case(state) `PROC_IF_WRITE_CIR:begin @@ -75,7 +95,13 @@ always @(negedge clock) begin state=`PROC_DE_STATE_ENTRY; end `PROC_EX_STATE_EXIT:begin - exec_unit_execute=1; + case(out_sel) + 2'b01:begin + reg_write=0; + end + default:begin + end + endcase state=`PROC_IF_STATE_ENTRY; end endcase @@ -92,6 +118,9 @@ always @(posedge clock) begin external_address_bus <= ProgCount; read <= 0; write <= 1; + reg_read_read=1; + reg_write=1; + ALU_OUT=1; state=`PROC_IF_WRITE_CIR; end `PROC_DE_STATE_ENTRY:begin @@ -105,8 +134,10 @@ always @(posedge clock) begin in1_sel=2'b00; in2_sel=2'b01; out_sel=2'b01; - PARAM2[2:0]=CIR[2:0]; - PARAM2[5:3]=CIR[2:0]; + reg_read_addr=CIR[2:0]; + reg_addr=CIR[2:0]; + reg_read_read=0; + ALU_OUT=0; state=`PROC_DE_LOAD_16_PARAM; end default:begin @@ -124,8 +155,10 @@ always @(posedge clock) begin in2_sel=2'b01; out_sel=2'b01; PARAM1=1; - PARAM2[2:0]=CIR[2:0]; - PARAM2[5:3]=CIR[2:0]; + reg_read_addr=CIR[2:0]; + reg_addr=CIR[2:0]; + reg_read_read=0; + ALU_OUT=0; state=`PROC_EX_STATE_ENTRY; end default:begin @@ -147,11 +180,13 @@ always @(posedge clock) begin state=`PROC_EX_STATE_ENTRY; end `PROC_EX_STATE_ENTRY:begin - EXCEPTION=0; - exec_unit_execute=0; + reg_data=ADDER16_1O; state=`PROC_EX_STATE_EXIT; + EXCEPTION=0; + end endcase end + endmodule diff --git a/cpu/registers.v b/cpu/registers.v index f4f8cc3..0e6d470 100644 --- a/cpu/registers.v +++ b/cpu/registers.v @@ -1,6 +1,6 @@ module register_file ( input [2:0]addr1, inout [15:0]data1, input wire read1, input wire write1 ,input [2:0]addr2,output [15:0]data2,input wire read2); reg [15:0] registers [7:0]; -assign data2 = !read2 ? registers[0] : 'b1111000011110000 ; +assign data2 = !read2 ? registers[0] : 'hz ; //assign data2 = !read2 ? registers[addr2]: 'b1111000011110000; assign data1 = !read1 ? registers[addr1]: 'hz; initial begin