2023-11-02 20:40:04 +00:00
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/* top.v - Implements FPGA and Board specific circuitry
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This file is part of the 9086 project.
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2024-02-10 15:52:13 +00:00
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Copyright (c) 2024 Efthymios Kritikos
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2023-11-02 20:40:04 +00:00
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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`include "error_header.v"
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2023-12-03 19:24:12 +00:00
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`ifdef OUTPUT_JSON_STATISTICS
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`include "config.v"
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`endif
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2023-11-02 20:40:04 +00:00
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module fpga_top(
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input clk48,
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2023-11-02 22:00:07 +00:00
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input user_button,
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2023-11-02 23:46:12 +00:00
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// output reset_n,
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2023-11-02 20:40:04 +00:00
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2023-11-02 23:46:12 +00:00
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output rgb_led0_r,
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output rgb_led0_g,
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output rgb_led0_b,
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2023-11-09 22:10:34 +00:00
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2023-12-07 16:39:04 +00:00
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`ifdef SYNTHESIS
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2023-12-03 19:24:12 +00:00
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output wire [15:0] ddram_a, // [15:13] are unused in litex as well, they just also route them through a trellis block
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output wire [2:0] ddram_ba,
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output wire ddram_cas_n,
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output wire ddram_cke,
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output wire ddram_clk_p,
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output wire ddram_cs_n,
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output wire [1:0] ddram_dm,
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input wire [15:0] ddram_dq,
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input wire [1:0] ddram_dqs_p,
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output wire [1:0] ddram_gnd,
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output wire ddram_odt,
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output wire ddram_ras_n,
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output wire ddram_reset_n,
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output wire [5:0] ddram_vccio,
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output wire ddram_we_n,
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2023-12-10 04:37:07 +00:00
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inout i2c_sda,/*sda*/
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output i2c_scl /*scl*/
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2023-12-07 16:39:04 +00:00
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`else
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output i2c_dir,
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output i2c_scl,
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input i2c_sda_in,
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output i2c_sda_out
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`endif
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2023-11-02 20:40:04 +00:00
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);
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2023-12-07 16:39:04 +00:00
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`ifndef SYNTHESIS
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string waveform_name;
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initial begin
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if($value$plusargs("WAVEFORM=%s",waveform_name))begin
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$dumpfile(waveform_name);
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$dumpvars(0,p,cycles);
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end
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end
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//TODO: should there be some common file between all the fpga_tops and system.v for this stuff?
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always @(posedge clk48) begin
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if(HALT==1&&disp_cache_start==disp_cache_end)begin
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$finish;
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end
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end
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reg sane;
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always @(posedge reset)begin sane<=1; end
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always @( ERROR ) begin
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if ( ERROR != `ERR_NO_ERROR && sane == 1 ) begin
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$display("PROCESSOR RUN INTO AN ERROR.");
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case (ERROR)
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default:begin
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end
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`ERR_UNIMPL_INSTRUCTION:begin
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$display("Unimplemented instruction");
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end
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`ERR_UNIMPL_ADDRESSING_MODE: begin
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$display("Unimplemented addressing mode");
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end
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endcase
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$finish;
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end
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end
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`endif
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`ifdef SYNTHESIS
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2023-12-03 19:24:12 +00:00
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assign ddram_a[15:13] = 3'b0;
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assign ddram_vccio = 6'd63;
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assign ddram_gnd = 2'd0;
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2023-12-07 16:39:04 +00:00
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`endif
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2023-12-03 19:24:12 +00:00
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2023-11-02 22:00:07 +00:00
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wire HALT;
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wire [`ERROR_BITS-1:0]ERROR;
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2023-11-02 23:46:12 +00:00
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wire [19:0] address_bus;
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wire [15:0] data_bus_read,data_bus_write;
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wire rd,wr,BHE,IOMEM;
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2023-11-09 22:10:34 +00:00
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2023-11-12 21:39:27 +00:00
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2023-12-03 19:24:12 +00:00
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wire CPU_SPEED;
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processor p(
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.clock(CPU_SPEED),
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.reset(reset),
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.HALT(HALT),
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.ERROR(ERROR),
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.external_address_bus(address_bus),
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.external_data_bus_read(data_bus_read),
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.external_data_bus_write(data_bus_write),
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.wait_state(wait_state),
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.read(rd),
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.write(wr),
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.BHE(BHE),
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.IOMEM(IOMEM)
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`ifdef CALCULATE_IPC
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/* STATISTICS */ ,.new_instruction(new_instruction)
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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/* */ ,.L1_SIZE_STAT(L1_SIZE_STAT), .VALID_INSTRUCTION_STAT(VALID_INSTRUCTION_STAT), .jump_req_debug(jump_req_debug)
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`endif
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2023-11-02 22:00:07 +00:00
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);
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2023-11-02 20:40:04 +00:00
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2023-12-07 16:39:04 +00:00
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/* verilator lint_off UNUSEDSIGNAL */
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2023-12-03 19:24:12 +00:00
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`ifdef CALCULATE_IPC
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wire new_instruction;
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`endif
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`ifdef OUTPUT_JSON_STATISTICS
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wire [`L1_CACHE_SIZE-1:0]L1_SIZE_STAT;
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wire VALID_INSTRUCTION_STAT;
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wire jump_req_debug;
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`endif
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2023-12-07 16:39:04 +00:00
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/* verilator lint_on UNUSEDSIGNAL */
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2023-11-02 23:46:12 +00:00
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reg [2:0]rgb_led_color;
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assign rgb_led0_r=rgb_led_color[0];
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assign rgb_led0_g=rgb_led_color[1];
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assign rgb_led0_b=rgb_led_color[2];
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2023-11-15 14:37:46 +00:00
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// A bit useless since if the cpu ERRORS out or HALTS it will continue executing anyway
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2023-11-06 08:12:58 +00:00
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//always @(HALT or ERROR or user_button) begin
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// if (HALT==1) begin
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// /* yellow */
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// rgb_led_color<=3'b100;
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// end else if (ERROR != `ERROR_BITS'b0) begin
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// /* red */
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// rgb_led_color<=3'b110;
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// end else begin
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// /* green */
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// rgb_led_color<=3'b101;
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// end
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//end
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2023-11-09 22:10:34 +00:00
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// Create a 27 bit register
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reg [26:0] counter = 0;
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2023-11-06 08:12:58 +00:00
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2023-11-09 22:10:34 +00:00
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// Every positive edge increment register by 1
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2023-11-06 08:12:58 +00:00
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always @(posedge clk48) begin
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counter <= counter + 1;
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end
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2023-11-09 22:10:34 +00:00
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/*** RESET CIRCUIT ***/
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2023-11-06 08:12:58 +00:00
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reg reset=0;
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reg [1:0] state=0;
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2023-11-12 07:28:51 +00:00
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always @(posedge counter[15]) begin
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2023-11-06 08:12:58 +00:00
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if(user_button==0)
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2023-12-03 19:24:12 +00:00
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state<=2'b00;
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2023-11-06 08:12:58 +00:00
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case (state)
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2'b00:begin
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reset<=0;
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state<=2'b01;
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end
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2'b01:begin
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reset<=1;
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state<=2'b10;
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end
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default: begin
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end
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endcase
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end
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2023-11-09 22:10:34 +00:00
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//------------------------------------------//
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// Cache to allow the slow display to have a
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// chance to keep up with the relentless CPU
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2024-02-09 23:28:21 +00:00
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reg [7:0] disp_cache_start=0;
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reg [7:0] disp_cache_end=0;
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reg [7:0] disp_write_cache [255:0];
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2023-11-09 22:10:34 +00:00
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reg ascii_state=0;
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2023-11-15 00:26:46 +00:00
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always @(posedge CPU_SPEED)begin
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if(wr==0)begin
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if(IOMEM==1'b1 && address_bus[7:0]==8'hA5 )begin
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disp_write_cache[disp_cache_end]<=data_bus_write[15:8];
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2024-02-09 23:28:21 +00:00
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disp_cache_end<=disp_cache_end+8'd1;
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2023-11-15 00:26:46 +00:00
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end else if(IOMEM==1'b1 && address_bus[7:0]==8'hB0 )begin
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if(data_bus_write[0:0]==1)
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2023-12-07 16:39:04 +00:00
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rgb_led_color<=3'b000;
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2023-11-15 00:26:46 +00:00
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else
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2023-12-07 16:39:04 +00:00
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rgb_led_color<=3'b111;
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2023-11-09 22:10:34 +00:00
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end
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2023-11-15 00:26:46 +00:00
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end else if(ascii_state==1'b0)begin
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if(ascii_data_ready&disp_cache_start!=disp_cache_end)begin
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2023-12-07 16:39:04 +00:00
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`ifndef SYNTHESIS
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$write("%s" ,disp_write_cache[disp_cache_start]); // TODO: maybe simulate the i2c lcd
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`endif
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2023-11-15 00:26:46 +00:00
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ascii_data<=disp_write_cache[disp_cache_start];
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2024-02-09 23:28:21 +00:00
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disp_cache_start<=disp_cache_start+8'd1;
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2023-11-15 00:26:46 +00:00
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ascii_data_write_req<=1;
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ascii_state<=1'b1;
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2023-11-09 22:10:34 +00:00
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end
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2023-11-15 00:26:46 +00:00
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end
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if(ascii_state==1'b1)begin
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if(!ascii_data_ready)begin
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ascii_data_write_req<=0;
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ascii_state<=1'b0;
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end
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end
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2023-11-09 22:10:34 +00:00
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end
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wire I2C_SPEED=counter[7];
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2023-12-03 19:24:12 +00:00
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wire [15:0]boot_rom_data_bus_read;
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wire [15:0]boot_rom_data_bus_write;
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assign boot_rom_data_bus_write=data_bus_write;
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wire boot_rom_cs_n;
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doublemem #( .RAM_SIZE_IN_BYTES(2048) ) boot_rom
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( address_bus[10:0],boot_rom_data_bus_read,boot_rom_data_bus_write,rd,wr,BHE,boot_rom_cs_n,CPU_SPEED );
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/// Memory Map
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assign data_bus_read = ( IOMEM == 1 ) ? data_bus_read_IO : data_bus_read_MEM ;
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2024-02-09 23:28:21 +00:00
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wire [15:0] data_bus_read_IO = ( address_bus[7:1] == 7'h10 ) ? LITEDRAM_STATUS_REGISTER : ( (address_bus[7:4] == 4'h4) ? Wishbone_driver_data_bus_read:CPU_I2C_data_bus_read);
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2023-12-03 19:24:12 +00:00
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assign boot_rom_cs_n = !((IOMEM==0)&&(address_bus[15:12]==4'hF));
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2024-02-09 23:28:21 +00:00
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wire [15:0] data_bus_read_MEM = (address_bus[15:12]==4'hF)? boot_rom_data_bus_read:data_bus_read_DDR3;
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2023-12-03 19:24:12 +00:00
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wire DDR3_ram_cs = (IOMEM==0)&&(address_bus[15:12]!=4'hF);
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//
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// 0x20 | DDR STATUS BYTE1 |
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// 0x21 | DDR STATUS BYTE1 |
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// | |
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// - | -- |
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// | |
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// 0x30 | WISHBONE |
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// .. | .. |
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// 0x3F | WISHBONE |
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//
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assign wishbone_cs=!((IOMEM==1)&&(address_bus[7:4] == 4'h4));
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2024-02-09 23:28:21 +00:00
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assign i2c_cs= !((IOMEM==1)&&(address_bus[7:4] == 4'h6));
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2023-12-03 19:24:12 +00:00
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2024-02-09 23:28:21 +00:00
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assign wait_state_I2C=(i2c_cs==1'b0&&rd==1'b0)^i2c_cs_1d;
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reg i2c_cs_1d;
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always @(posedge CPU_SPEED)begin
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i2c_cs_1d<=(i2c_cs==1'b0&&rd==1'b0);
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end // TODO: Probably would need to so the same for the wishbone IO
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wire wait_state_I2C;
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2023-12-03 19:24:12 +00:00
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/// DDR3 Controller
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wire ddr3_init_done,ddr3_init_error,ddr3_pll_locked;
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2023-12-07 16:39:04 +00:00
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/* verilator lint_off UNUSEDSIGNAL */
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wire user_rst;
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/* verilator lint_on UNUSEDSIGNAL */
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`ifndef SYNTHESIS
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assign ddr3_pll_locked=1;
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wire sim_trace;
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assign sim_trace=0;//signal is not connected on litedram, not sure what was the idea behind it
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`endif
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2023-12-03 19:24:12 +00:00
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wire [15:0]Wishbone_driver_data_bus_read;
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wire [15:0]Wishbone_driver_data_bus_write=data_bus_write;
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wire wishbone_cs;
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Wishbone_IO_driver Wishbone_IO_driver(
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///// GENERAL //////
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.clock(CPU_SPEED),
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.reset_n(reset),
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////// CPU INTERFACE ///////
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.address(address_bus[3:1]),
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.data_bus_in(Wishbone_driver_data_bus_write),
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.data_bus_out(Wishbone_driver_data_bus_read),
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.read_n(rd),
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.write_n(wr),
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.chip_select_n(wishbone_cs),
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////// WISHBONE INTERFACE /////
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.wb_ctrl_ack(wb_ctrl_ack),
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.wb_ctrl_adr(wb_ctrl_adr),
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.wb_ctrl_cyc(wb_ctrl_cyc),
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|
|
.wb_ctrl_err(wb_ctrl_err),
|
|
|
|
.wb_ctrl_sel(wb_ctrl_sel),
|
|
|
|
.wb_ctrl_stb(wb_ctrl_stb),
|
|
|
|
.wb_ctrl_we(wb_ctrl_we),
|
|
|
|
.wb_ctrl_bte(wb_ctrl_bte),
|
|
|
|
.wb_ctrl_cti(wb_ctrl_cti),
|
|
|
|
.wb_ctrl_dat_r(wb_ctrl_dat_r),
|
|
|
|
.wb_ctrl_dat_w(wb_ctrl_dat_w)
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
wire [15:0] LITEDRAM_STATUS_REGISTER = { 13'd0, ddr3_pll_locked ,ddr3_init_error, ddr3_init_done };
|
|
|
|
wire [15:0] data_bus_read_DDR3;
|
|
|
|
|
|
|
|
Wishbone_memory_driver Wishbone_memory_driver(
|
|
|
|
///// GENERAL //////
|
|
|
|
.clock(CPU_SPEED),
|
|
|
|
.reset_n(reset),
|
|
|
|
|
|
|
|
////// CPU INTERFACE ///////
|
|
|
|
.address(address_bus),
|
2023-12-05 02:49:28 +00:00
|
|
|
.BHE(BHE),
|
2023-12-03 19:24:12 +00:00
|
|
|
.data_bus_in(data_bus_write),
|
|
|
|
.data_bus_out(data_bus_read_DDR3),
|
2024-02-09 23:28:21 +00:00
|
|
|
.wait_state(wait_state_WBIO),
|
2023-12-03 19:24:12 +00:00
|
|
|
.read_n(rd),
|
|
|
|
.write_n(wr),
|
2023-12-05 02:49:28 +00:00
|
|
|
.chip_select_n(!(DDR3_ram_cs&&ddr3_init_done)),
|
2023-12-03 19:24:12 +00:00
|
|
|
|
|
|
|
////// WISHBONE INTERFACE /////
|
|
|
|
.wb_mem_ack(wb_mem_ack),
|
|
|
|
.wb_mem_adr(wb_mem_adr),
|
|
|
|
.wb_mem_cyc(wb_mem_cyc),
|
|
|
|
.wb_mem_err(wb_mem_err),
|
|
|
|
.wb_mem_sel(wb_mem_sel),
|
|
|
|
.wb_mem_stb(wb_mem_stb),
|
|
|
|
.wb_mem_we(wb_mem_we),
|
|
|
|
.wb_mem_data_r(wb_mem_data_r),
|
|
|
|
.wb_mem_data_w(wb_mem_data_w)
|
|
|
|
);
|
|
|
|
|
|
|
|
wire wait_state;
|
2024-02-09 23:28:21 +00:00
|
|
|
assign wait_state=wait_state_WBIO||wait_state_I2C;
|
|
|
|
wire wait_state_WBIO;
|
2023-12-03 19:24:12 +00:00
|
|
|
|
|
|
|
wire wb_ctrl_ack;
|
|
|
|
wire [29:0] wb_ctrl_adr;
|
|
|
|
wire [1:0] wb_ctrl_bte;
|
|
|
|
wire [2:0] wb_ctrl_cti;
|
|
|
|
wire wb_ctrl_cyc;
|
|
|
|
wire [31:0] wb_ctrl_dat_r;
|
|
|
|
wire [31:0] wb_ctrl_dat_w;
|
|
|
|
wire wb_ctrl_err;
|
|
|
|
wire [3:0] wb_ctrl_sel;
|
|
|
|
wire wb_ctrl_stb;
|
|
|
|
wire wb_ctrl_we;
|
|
|
|
|
|
|
|
wire wb_mem_ack;
|
|
|
|
wire [24:0] wb_mem_adr;
|
|
|
|
wire wb_mem_cyc;
|
|
|
|
wire [31:0] wb_mem_data_r;
|
|
|
|
wire [31:0] wb_mem_data_w;
|
|
|
|
wire wb_mem_err;
|
|
|
|
wire [3:0] wb_mem_sel;
|
|
|
|
wire wb_mem_stb;
|
|
|
|
wire wb_mem_we;
|
|
|
|
|
|
|
|
litedram_core DDR3_RAM_DRIVER(
|
|
|
|
////// GENERAL ///////
|
|
|
|
.clk(clk48),
|
|
|
|
.user_clk(CPU_SPEED),
|
2023-12-07 16:39:04 +00:00
|
|
|
`ifdef SYNTHESIS
|
2023-12-03 19:24:12 +00:00
|
|
|
.rst(!reset),
|
2023-12-07 16:39:04 +00:00
|
|
|
.pll_locked(ddr3_pll_locked),
|
|
|
|
`else
|
|
|
|
.sim_trace(sim_trace),
|
|
|
|
`endif
|
2023-12-03 19:24:12 +00:00
|
|
|
|
|
|
|
////// DDR3 INTERFACE //////
|
2023-12-07 16:39:04 +00:00
|
|
|
`ifdef SYNTHESIS
|
2023-12-03 19:24:12 +00:00
|
|
|
.ddram_a(ddram_a[12:0]), //also ignored on the litedram core
|
|
|
|
.ddram_ba(ddram_ba),
|
|
|
|
.ddram_cas_n(ddram_cas_n),
|
|
|
|
.ddram_cke(ddram_cke),
|
|
|
|
.ddram_clk_n(1'b0), // goes nowhere ...
|
|
|
|
.ddram_clk_p(ddram_clk_p),
|
|
|
|
.ddram_cs_n(ddram_cs_n),
|
|
|
|
.ddram_dm(ddram_dm),
|
|
|
|
.ddram_dq(ddram_dq),
|
|
|
|
.ddram_dqs_n(2'b00), // goes nowhere ...
|
|
|
|
.ddram_dqs_p(ddram_dqs_p),
|
|
|
|
.ddram_odt(ddram_odt),
|
|
|
|
.ddram_ras_n(ddram_ras_n),
|
|
|
|
.ddram_reset_n(ddram_reset_n),
|
|
|
|
.ddram_we_n(ddram_we_n),
|
2023-12-07 16:39:04 +00:00
|
|
|
`endif
|
2023-12-03 19:24:12 +00:00
|
|
|
|
|
|
|
/////// SYSTEM MEMORY INTERFACE ////////////////
|
|
|
|
.init_done(ddr3_init_done),
|
|
|
|
.init_error(ddr3_init_error),
|
|
|
|
.user_port_wishbone_0_ack(wb_mem_ack),
|
|
|
|
.user_port_wishbone_0_adr(wb_mem_adr),
|
|
|
|
.user_port_wishbone_0_cyc(wb_mem_cyc),
|
|
|
|
.user_port_wishbone_0_dat_r(wb_mem_data_r),
|
|
|
|
.user_port_wishbone_0_dat_w(wb_mem_data_w),
|
|
|
|
.user_port_wishbone_0_err(wb_mem_err),
|
|
|
|
.user_port_wishbone_0_sel(wb_mem_sel),
|
|
|
|
.user_port_wishbone_0_stb(wb_mem_stb),
|
|
|
|
.user_port_wishbone_0_we(wb_mem_we),
|
2023-12-07 16:39:04 +00:00
|
|
|
.user_rst(user_rst),
|
2023-12-03 19:24:12 +00:00
|
|
|
|
|
|
|
/////// WISHBONE CONTROL INTERFACE ///////////
|
|
|
|
.wb_ctrl_ack(wb_ctrl_ack),
|
|
|
|
.wb_ctrl_adr(wb_ctrl_adr),
|
|
|
|
.wb_ctrl_cyc(wb_ctrl_cyc),
|
|
|
|
.wb_ctrl_err(wb_ctrl_err),
|
|
|
|
.wb_ctrl_sel(wb_ctrl_sel),
|
|
|
|
.wb_ctrl_stb(wb_ctrl_stb),
|
|
|
|
.wb_ctrl_we(wb_ctrl_we),
|
|
|
|
.wb_ctrl_bte(wb_ctrl_bte),
|
|
|
|
.wb_ctrl_cti(wb_ctrl_cti),
|
|
|
|
.wb_ctrl_dat_r(wb_ctrl_dat_r),
|
|
|
|
.wb_ctrl_dat_w(wb_ctrl_dat_w)
|
|
|
|
);
|
|
|
|
|
2024-02-09 23:28:21 +00:00
|
|
|
wire [15:0]CPU_I2C_data_bus_read;
|
|
|
|
wire i2c_cs;
|
|
|
|
|
|
|
|
wire [6:0] CPU_I2C_OUT_ADDRESS;
|
|
|
|
wire CPU_I2C_OUT_BUSY,CPU_I2C_OUT_TRANSACT,CPU_I2C_DIR;
|
|
|
|
wire [15:0]CPU_I2C_DATA_READ,CPU_I2C_DATA_WRITE;
|
|
|
|
wire CPU_I2C_IGN_ACK;
|
2024-02-10 22:35:33 +00:00
|
|
|
wire CPU_I2C_ERROR;
|
2024-02-09 23:28:21 +00:00
|
|
|
|
|
|
|
CPU_to_I2C_driver_bridge CPU_to_I2C_driver_bridge (
|
|
|
|
.clock(CPU_SPEED),
|
|
|
|
.reset_n(reset),
|
|
|
|
|
|
|
|
// CPU INTERFACE
|
|
|
|
.address(address_bus[2:0]),
|
|
|
|
.data_bus_in(data_bus_write),
|
|
|
|
.data_bus_out(CPU_I2C_data_bus_read),
|
|
|
|
.read_n(rd),
|
|
|
|
.write_n(wr),
|
|
|
|
.chip_select_n(i2c_cs),
|
|
|
|
|
|
|
|
// I2C DRIVER INTERFACE
|
|
|
|
.OUT_ADDRESS(CPU_I2C_OUT_ADDRESS),
|
|
|
|
.OUT_BUSY(CPU_I2C_OUT_BUSY),
|
|
|
|
.OUT_TRANSACT(CPU_I2C_OUT_TRANSACT),
|
|
|
|
.DIR(CPU_I2C_DIR),
|
|
|
|
.OUT_I2C_DATA_READ(CPU_I2C_DATA_READ),
|
|
|
|
.OUT_I2C_DATA_WRITE(CPU_I2C_DATA_WRITE),
|
|
|
|
|
|
|
|
.TRANS_WIDTH(CPU_I2C_TRANS_WIDTH),
|
2024-02-10 22:35:33 +00:00
|
|
|
.OUT_IGN_ACK(CPU_I2C_IGN_ACK),
|
|
|
|
.IN_ERROR(CPU_I2C_ERROR)
|
2024-02-09 23:28:21 +00:00
|
|
|
);
|
|
|
|
|
2023-11-09 22:10:34 +00:00
|
|
|
// Display driver
|
|
|
|
|
|
|
|
wire ascii_data_ready;
|
|
|
|
reg ascii_data_write_req=0;
|
|
|
|
reg [7:0] ascii_data;
|
|
|
|
ascii_to_HD44780_driver LCD_DRIVER(
|
|
|
|
/* system */
|
|
|
|
I2C_SPEED,
|
|
|
|
1'b1,
|
|
|
|
|
|
|
|
/* Data Input */
|
|
|
|
ascii_data_ready,
|
|
|
|
ascii_data_write_req,
|
|
|
|
ascii_data,
|
|
|
|
|
|
|
|
/* write circuitry */
|
|
|
|
!pcf_busy,
|
|
|
|
pcf_write_req,
|
|
|
|
pcf_data,
|
|
|
|
pcf_command_data
|
|
|
|
);
|
|
|
|
|
|
|
|
// Port expander driver
|
|
|
|
|
|
|
|
wire pcf_write_req,pcf_command_data,pcf_busy;
|
|
|
|
wire [3:0]pcf_data;
|
2024-02-09 23:28:21 +00:00
|
|
|
/* verilator lint_off UNUSEDSIGNAL */
|
|
|
|
wire [7:0]DISP_I2C_DATA_WRITE;
|
|
|
|
wire [15:0]DISP_I2C_DATA_READ;
|
|
|
|
/* verilator lint_on UNUSEDSIGNAL */
|
|
|
|
wire DISP_I2C_BUSY,DISP_I2C_TRANSACT;
|
|
|
|
wire [6:0] DISP_I2C_ADDRESS;
|
|
|
|
assign DISP_I2C_ADDRESS=7'h27;
|
|
|
|
wire DISP_DIR;
|
2023-11-09 22:10:34 +00:00
|
|
|
|
|
|
|
pcf8574_for_HD44780 PCF8574_driver(
|
|
|
|
.clock(I2C_SPEED),
|
|
|
|
|
|
|
|
.pcf_write_req(pcf_write_req),
|
|
|
|
.pcf_command_data(pcf_command_data),
|
|
|
|
.pcf_data(pcf_data),
|
|
|
|
|
|
|
|
.pcf_busy(pcf_busy),
|
|
|
|
.new_backlight(1'b0),
|
|
|
|
.backlight_update(1'b0),
|
|
|
|
|
2024-02-09 23:28:21 +00:00
|
|
|
.DIR(DISP_DIR),
|
|
|
|
.I2C_BUSY(DISP_I2C_BUSY),
|
|
|
|
.I2C_TRANSACT(DISP_I2C_TRANSACT),
|
|
|
|
|
|
|
|
.i2c_data_write(DISP_I2C_DATA_WRITE)
|
|
|
|
);
|
|
|
|
|
|
|
|
wire [6:0]MULT_TO_DRIV_I2C_ADDRESS;
|
|
|
|
wire MULT_TO_DRIV_I2C_BUSY;
|
|
|
|
wire MULT_TO_DRIV_I2C_TRANSACT;
|
|
|
|
wire [15:0]MULT_TO_DRIV_DATA_WRITE, MULT_TO_DRIV_DATA_READ;
|
|
|
|
wire MULT_TO_DRIV_DIR;
|
|
|
|
wire CPU_I2C_TRANS_WIDTH;
|
|
|
|
|
2024-02-26 13:12:26 +00:00
|
|
|
/* verilator lint_off UNUSEDSIGNAL */
|
|
|
|
wire DISP_ERROR; //TODO: It would be ideal to acknoledge any warnings but it's not really too important
|
|
|
|
/* verilator lint_on UNUSEDSIGNAL */
|
|
|
|
|
2024-02-09 23:28:21 +00:00
|
|
|
I2C_driver_multiplexer I2C_driver_multiplexer(
|
|
|
|
.clock(I2C_SPEED),
|
|
|
|
.reset_n(reset),
|
2023-11-09 22:10:34 +00:00
|
|
|
|
2024-02-09 23:28:21 +00:00
|
|
|
////// INPUT 1 ///////
|
|
|
|
.IN1_ADDRESS(DISP_I2C_ADDRESS),
|
|
|
|
.IN1_BUSY(DISP_I2C_BUSY),
|
|
|
|
.IN1_DIR(DISP_DIR),
|
|
|
|
.IN1_TRANSACT(DISP_I2C_TRANSACT),
|
|
|
|
.IN1_I2C_DATA_READ(DISP_I2C_DATA_READ),
|
|
|
|
.IN1_I2C_DATA_WRITE({8'h0,DISP_I2C_DATA_WRITE}),
|
|
|
|
.IN1_TRANS_WIDTH(1'b0),
|
|
|
|
.IN1_IGN_ACK(1'b0),
|
2024-02-26 13:12:26 +00:00
|
|
|
.IN1_ERROR(DISP_ERROR),
|
2024-02-09 23:28:21 +00:00
|
|
|
|
|
|
|
////// INPUT 2 ///////
|
|
|
|
.IN2_ADDRESS(CPU_I2C_OUT_ADDRESS),
|
|
|
|
.IN2_BUSY(CPU_I2C_OUT_BUSY),
|
|
|
|
.IN2_TRANSACT(CPU_I2C_OUT_TRANSACT),
|
|
|
|
.IN2_DIR(CPU_I2C_DIR),
|
|
|
|
.IN2_I2C_DATA_READ(CPU_I2C_DATA_READ),
|
|
|
|
.IN2_I2C_DATA_WRITE(CPU_I2C_DATA_WRITE),
|
|
|
|
.IN2_TRANS_WIDTH(CPU_I2C_TRANS_WIDTH),
|
|
|
|
.IN2_IGN_ACK(CPU_I2C_IGN_ACK),
|
2024-02-10 22:35:33 +00:00
|
|
|
.IN2_ERROR(CPU_I2C_ERROR),
|
2024-02-09 23:28:21 +00:00
|
|
|
|
|
|
|
////// OUTPUT ///////
|
|
|
|
.OUT_ADDRESS(MULT_TO_DRIV_I2C_ADDRESS),
|
|
|
|
.OUT_BUSY(MULT_TO_DRIV_I2C_BUSY),
|
|
|
|
.OUT_TRANSACT(MULT_TO_DRIV_I2C_TRANSACT),
|
|
|
|
.OUT_DIR(MULT_TO_DRIV_DIR),
|
|
|
|
.OUT_I2C_DATA_WRITE(MULT_TO_DRIV_DATA_WRITE),
|
|
|
|
.OUT_I2C_DATA_READ(MULT_TO_DRIV_DATA_READ),
|
|
|
|
.OUT_TRANS_WIDTH(MULT_TO_DRIV_TRANS_WIDTH),
|
2024-02-10 22:35:33 +00:00
|
|
|
.OUT_IGN_ACK(MULT_TO_DRIV_IGN_ACK),
|
|
|
|
.OUT_ERROR(MULT_TO_DRIV_ERROR)
|
2023-11-09 22:10:34 +00:00
|
|
|
);
|
|
|
|
|
|
|
|
// I2C driver
|
|
|
|
|
2023-12-07 16:39:04 +00:00
|
|
|
wire SDA_direction;
|
2024-02-09 23:28:21 +00:00
|
|
|
wire SCL,SDA_input,SDA_output;
|
|
|
|
wire MULT_TO_DRIV_TRANS_WIDTH;
|
|
|
|
wire MULT_TO_DRIV_IGN_ACK;
|
2024-02-10 22:35:33 +00:00
|
|
|
wire MULT_TO_DRIV_ERROR;
|
2023-11-15 00:26:46 +00:00
|
|
|
|
2023-11-09 22:10:34 +00:00
|
|
|
I2C_driver i2c_driver(
|
|
|
|
.clock(I2C_SPEED),
|
|
|
|
|
2023-12-04 22:40:53 +00:00
|
|
|
.SDA_input(SDA_input),
|
|
|
|
.SDA_output(SDA_output),
|
|
|
|
.SDA_direction(SDA_direction),
|
2023-11-09 22:10:34 +00:00
|
|
|
.SCL(SCL),
|
|
|
|
|
2024-02-09 23:28:21 +00:00
|
|
|
.address(MULT_TO_DRIV_I2C_ADDRESS),
|
|
|
|
.I2C_BUSY(MULT_TO_DRIV_I2C_BUSY),
|
|
|
|
.I2C_TRANSACT(MULT_TO_DRIV_I2C_TRANSACT),
|
|
|
|
.DIR(MULT_TO_DRIV_DIR),
|
|
|
|
.i2c_data_write(MULT_TO_DRIV_DATA_WRITE),
|
|
|
|
.i2c_data_read(MULT_TO_DRIV_DATA_READ),
|
|
|
|
|
|
|
|
.transact_width(MULT_TO_DRIV_TRANS_WIDTH),
|
2024-02-10 22:35:33 +00:00
|
|
|
.ignore_ack(MULT_TO_DRIV_IGN_ACK),
|
|
|
|
|
|
|
|
.error(MULT_TO_DRIV_ERROR)
|
2023-11-09 22:10:34 +00:00
|
|
|
);
|
|
|
|
|
2023-12-07 16:39:04 +00:00
|
|
|
`ifdef SYNTHESIS
|
|
|
|
|
2023-12-04 22:40:53 +00:00
|
|
|
TRELLIS_IO #(
|
|
|
|
// Parameters.
|
|
|
|
.DIR ("BIDIR")
|
|
|
|
) TRELLIS_IO_00 (
|
|
|
|
// pin
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2023-12-10 04:37:07 +00:00
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.B (i2c_sda),
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2023-12-04 22:40:53 +00:00
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//input
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.I (1'd0),
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//Direction
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.T (~( SDA_direction & (~SDA_output) )),
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// Output
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.O (SDA_input)
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);
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2023-12-10 04:37:07 +00:00
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assign i2c_scl=SCL;
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2023-12-07 16:39:04 +00:00
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`else
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assign i2c_dir=SDA_direction;
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assign i2c_scl=SCL;
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assign SDA_input=i2c_sda_in;
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assign i2c_sda_out=SDA_output;
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`endif
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2023-12-04 22:40:53 +00:00
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2023-11-02 22:00:07 +00:00
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endmodule
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