| .. |
|
external_ip
|
Added .keep file for intentionally empty directory
|
2023-12-03 19:30:59 +00:00 |
|
fpga_config/OrangeCrab_r0.2.1
|
Project: Fixed verilator warnings for fpga_sim
|
2024-02-26 13:12:26 +00:00 |
|
peripherals
|
Project: Fixed verilator warnings for fpga_sim
|
2024-02-26 13:12:26 +00:00 |
|
alu_header.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
alu.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
biu.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
boot_code.asm
|
Peripherals/Memory: Added support for the litedram DDR memory controller, created a new memory map and updated all relevant code and files including the addition of rudimentary wait state support for the cpu (BIU)
|
2023-12-03 19:24:39 +00:00 |
|
config.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
decoder.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
error_header.v
|
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
|
2023-05-07 13:34:15 +01:00 |
|
exec_state_def.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
execute.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
general.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
Makefile
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
memory.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
processor.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
registers.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
system.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
testbench.cpp
|
Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
|
2023-11-04 11:04:22 +00:00 |
|
testbench.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
ucode_header.v
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
ucode.txt
|
Project: updated copyright notices and README and fixed a few spelling mistakes
|
2024-02-10 15:52:13 +00:00 |
|
verilator_makefile
|
Removed erroneous file and run aspell
|
2023-03-21 14:51:39 +00:00 |
|
verilator_makefile_fpga
|
Build system: Small fixes and corrected rebuild when only the verilator testbench was changed
|
2023-12-09 02:39:14 +00:00 |
