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9086/gtkwave_savefile.gtkw

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Basic start for the control block
2023-02-08 09:18:00 +00:00
[*]
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
[*] GTKWave Analyzer v3.3.111 (w)1999-2020 BSI
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
[*] Sun May 7 11:35:53 2023
Basic start for the control block
2023-02-08 09:18:00 +00:00
[*]
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
2023-03-09 06:02:41 +00:00
[dumpfile] "/home/user/9086/system/boot_code.fst"
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
[dumpfile_mtime] "Sun May 7 11:35:19 2023"
[dumpfile_size] 13013
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
[savefile] "/home/user/9086/gtkwave_savefile.gtkw"
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
[timestart] 500000000
[size] 1524 993
Basic start for the control block
2023-02-08 09:18:00 +00:00
[pos] -1 -1
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
*-36.395050 127070000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
[treeopen] TOP.
[treeopen] TOP.system.
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
[treeopen] TOP.system.p.
[treeopen] TOP.system.p.BIU.
[sst_width] 263
Added ROM, address and data buses and primitive program counter
2023-02-08 11:57:22 +00:00
[signals_width] 293
Basic start for the control block
2023-02-08 09:18:00 +00:00
[sst_expanded] 1
Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
2023-02-22 01:28:23 +00:00
[sst_vpaned_height] 312
Implemented a basic Instruction Fetch stage and added some examples in the 8086 doc
2023-02-08 23:59:06 +00:00
@28
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
TOP.system.clock
TOP.system.reset
Added a very basic execution stage, registers and a very crude adder for ALU. It finally executes instructions!
2023-02-09 20:16:50 +00:00
@22
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
TOP.system.address_bus[19:0]
TOP.system.data_bus[15:0]
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
TOP.system.p.BIU.biu_state[3:0]
Added support for writing to memory
2023-02-14 13:13:40 +00:00
@28
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
TOP.system.p.read
TOP.system.p.write
Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
2023-03-09 06:02:41 +00:00
TOP.system.IOMEM
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
TOP.system.p.ERROR[2:0]
TOP.system.p.HALT
@29
TOP.system.p.state[3:0]
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
@22
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
TOP.system.p.BIU.INSTRUCTION[31:0]
Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
2023-03-05 00:10:55 +00:00
@28
First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
2023-05-07 12:34:15 +00:00
TOP.system.p.BIU.VALID_INSTRUCTION
TOP.system.p.BIU.NEXT_POSITION[1:0]
@22
TOP.system.p.BIU.FIFO_end[3:0]
TOP.system.p.BIU.FIFO_start[3:0]
TOP.system.p.BIU.INPUT_FIFO[0][7:0]
TOP.system.p.BIU.INPUT_FIFO[1][7:0]
TOP.system.p.BIU.INPUT_FIFO[2][7:0]
TOP.system.p.BIU.INPUT_FIFO[3][7:0]
TOP.system.p.BIU.INPUT_FIFO[4][7:0]
TOP.system.p.BIU.INPUT_FIFO[5][7:0]
TOP.system.p.BIU.INPUT_FIFO[6][7:0]
TOP.system.p.BIU.INPUT_FIFO[7][7:0]
TOP.system.p.BIU.INPUT_FIFO[8][7:0]
TOP.system.p.BIU.INPUT_FIFO[9][7:0]
TOP.system.p.BIU.INPUT_FIFO[10][7:0]
TOP.system.p.BIU.INPUT_FIFO[11][7:0]
TOP.system.p.BIU.INPUT_FIFO[12][7:0]
TOP.system.p.BIU.INPUT_FIFO[13][7:0]
TOP.system.p.BIU.INPUT_FIFO[14][7:0]
TOP.system.p.BIU.INPUT_FIFO[15][7:0]
TOP.system.p.ucode_seq_addr[4:0]
Basic start for the control block
2023-02-08 09:18:00 +00:00
[pattern_trace] 1
[pattern_trace] 0
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