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da51dd6da7
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First draft of a bus interface unit in an effort to make the CPU pipelined. Currently supports code prefetching
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2023-05-07 13:34:15 +01:00 |
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11624ca2d2
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Added the OUT instruction to be able to properly address I/O and moved printing logic to a device on the I/O space. Also added IRET which is basically just a RET in this case
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2023-03-09 06:03:13 +00:00 |
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99cbc49e95
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Wrote a more complete testbench for verilator, switched from lx2 to fst and fixed cpu clock frequency calculation
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2023-03-05 00:10:55 +00:00 |
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7fde422341
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Added Microcode support, Stack, implemented the CALL instruction in microcode and grouped the wires on the decoder module
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2023-02-22 01:28:23 +00:00 |
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ded47555a5
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Improved build system and project directory structure
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2023-02-16 01:52:02 +00:00 |
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