(Tim) Efthimis Kritikos Efthimis
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Efthimis pushed to master at Efthimis/9086 2023-11-06 08:13:07 +00:00
01dcbfa7a1 The CPU works on real hardware for the first time! I added an adjustment for ram size, added control for a led and a test program for it. On the fpga board there is an actual led there that I used to verify functionality
Efthimis pushed to master at Efthimis/9086 2023-11-06 05:35:47 +00:00
30ffa1b00c Fixed a "combinatorial loop" and now if the build-in memory is reduced the design can be synthesized!
Efthimis pushed to master at Efthimis/9086 2023-11-06 01:35:50 +00:00
5ebd53b11c fixed more driver conflicts
Efthimis pushed to master at Efthimis/9086 2023-11-05 20:17:37 +00:00
ae16c79b0a Fixed another driver conflict
Efthimis pushed to master at Efthimis/9086 2023-11-05 19:43:31 +00:00
9947517693 Fixed simulation with icarus verilog and removed another driver conflict
Efthimis pushed to master at Efthimis/9086 2023-11-05 16:22:49 +00:00
4a5df9c74e Fixed another driver conflict
Efthimis pushed to master at Efthimis/9086 2023-11-04 15:33:24 +00:00
aa9b7c0a50 Removed more "conflicting driver" issues with yet more performance penalties...
Efthimis pushed to master at Efthimis/9086 2023-11-04 11:04:09 +00:00
df2975fa09 Fixed a lot of "conflicting driver" issues but I had to roll back an optimisation
Efthimis pushed to master at Efthimis/9086 2023-11-04 08:30:32 +00:00
c7ddf3fa9e More small fixes
Efthimis pushed to master at Efthimis/9086 2023-11-04 08:08:30 +00:00
694f708a32 Fixed some relatively low hanging fruit
Efthimis pushed to master at Efthimis/9086 2023-11-04 06:59:58 +00:00
85bdf9f87e Fixed some relatively low hanging fruit in regards to synthesisability
Efthimis pushed to master at Efthimis/9086 2023-11-02 23:45:38 +00:00
934e2f5a36 Fixed a bunch of things wrong with fpga_top.v and gated off some more simulation-only code
Efthimis pushed to master at Efthimis/9086 2023-11-02 22:18:45 +00:00
08aac5c7b6 Removed some code that wasn't meant for synthesis and fixed important bug in Makefile
Efthimis pushed to master at Efthimis/9086 2023-11-02 21:59:35 +00:00
601397b7f0 Properly added fpga_top.v stuff in the build system and fixed some syntax errors
Efthimis pushed to master at Efthimis/9086 2023-11-02 21:47:44 +00:00
43f3e16ca4 Removed all instances of inout since from what i understand it's mostly synthesisable
Efthimis pushed to master at Efthimis/9086 2023-11-02 20:39:37 +00:00
36bf8f9c7a Added OrangeCrab board-specific code to connect the cpu to the outside world
Efthimis pushed to master at Efthimis/9086 2023-11-02 00:28:43 +00:00
5feee9de57 Added support to the build system for synthesising, place and routing, serialising and uploading the design to a Lattice ECP5 OrangeCrab FPGA
Efthimis pushed to master at Efthimis/9086 2023-11-02 00:28:16 +00:00
Efthimis pushed to master at Efthimis/9086 2023-11-02 00:23:11 +00:00
6b9d0c49fb Added support for synthesising, place and routing, serialising and uploading the design on to a Lattice ECP5 OrangeCrab FPGA
Efthimis pushed to master at Efthimis/Testing 2023-11-02 00:11:14 +00:00
440b55f4d0 Test