(Tim) Efthimis Kritikos Efthimis
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Efthimis pushed to master at Efthimis/9086 2023-05-17 20:30:17 +00:00
7db70d79ff Made execute unit start at a state transition of a signal from the decoder thus allowing for an IPC of 0.99 !!
Efthimis pushed to master at Efthimis/9086 2023-05-17 19:08:34 +00:00
90f63b525d Made the decode unit able to continuously decode (simple) instructions if BIU allows it
Efthimis pushed to master at Efthimis/9086 2023-05-17 10:03:48 +00:00
30c3deca37 Made the execute unit signal the end of execution by a state change rather than the state of a signal to allow for one cycle instructions
Efthimis pushed to master at Efthimis/9086 2023-05-16 17:06:10 +00:00
53e9d371d7 Fully optimised BIU. Now it can instantly deliver instructions back to back
Efthimis pushed to master at Efthimis/9086 2023-05-16 15:30:15 +00:00
f914d1ec8f Cleaned up processor.v a bit
Efthimis pushed to master at Efthimis/9086 2023-05-16 13:04:32 +00:00
aca3357cda Fixed README formatting error
Efthimis pushed to master at Efthimis/Testing 2023-05-16 13:03:23 +00:00
95dc7a8d27 aaa
Efthimis pushed to master at Efthimis/Testing 2023-05-16 13:02:33 +00:00
cd81f846a9 test main readme
Efthimis pushed to master at Efthimis/9086 2023-05-16 12:57:56 +00:00
97912b1a29 Fixed bug found by icarus verilog and added outdated notice to README
Efthimis pushed to master at Efthimis/9086 2023-05-16 12:31:40 +00:00
bfa576e2a0 Cleaned up the interface between BIU and the processor
Efthimis pushed to master at Efthimis/9086 2023-05-14 15:05:00 +00:00
07d2a80b2e Added code to record statistics and a tool to plot them
Efthimis pushed to master at Efthimis/9086 2023-05-13 12:43:46 +00:00
df342467c7 Saved a clock cycle from microcode starts and added info in decode to allow saving a cycle on almost every instruction
Efthimis pushed to master at Efthimis/9086 2023-05-13 10:00:01 +00:00
00aa828ddc Improved parallelism
Efthimis pushed to master at Efthimis/9086 2023-05-13 05:53:38 +00:00
fe0426a77b Made execute unit run in parallel with everything else. Still not parallel for most of the time though
Efthimis pushed to master at Efthimis/9086 2023-05-11 18:54:28 +00:00
7151d5634f Fixed bug that prevented Icarus Verilog from simulating correctly
Efthimis pushed to master at Efthimis/9086 2023-05-11 15:26:55 +00:00
539fb8416b Fixed copyright notices, did some major cleanup and bumped README's versions
Efthimis pushed to master at Efthimis/9086 2023-05-11 11:21:34 +00:00
a8ab6b2dc7 Separated the execution unit from decode
Efthimis pushed to master at Efthimis/9086 2023-05-10 07:52:09 +00:00
7724e5f383 Removed deprecated BIU_NEXT_POSITION
Efthimis pushed to master at Efthimis/9086 2023-05-10 07:33:48 +00:00
e4ef199b83 Fixed a memory corruption bug
7e612bb701 made BIU snoop into the processor to deliver new instructions faster and fixed some bugs
c854818d6d Tightened up write timing
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Efthimis pushed to master at Efthimis/9086 2023-05-10 03:04:32 +00:00
b7bfbd4e33 Improved BIU performance and debug messages