Testing/test.md

A CPU that aims to be binary compatible with the 8086 ISA, focused on optimisation and flexibility.

Progress

• 8086
  • Executing code
  • Is Turing complete
  • Can boot up MS-DOS / FreeDOS
  • Is completely binary compatible
  • Is pipelined
  • Is Out of Order
  • Is superscalar
  • Has been successfully synthesized

High level design overview

Simulating it

Both Verilator and Icarus Verilog can be used for simulation. You can select which one you want with the SIM variable on common.mk Specifically this list shows the software needed and the versions used during development (other versions should work as well)

• Icarus Verilog : version 12.0 OR (preferred) Verilator : 5.016
• bin86 : 0.16.21
• GNU Make : 4.4.1
• xxd : 2022-01-14
• POSIX coreutils : GNU coreutils 9.4

After that you can run make on the top level directory and it should build everything and start the simulation

Synthesis and bitstream creation ( for FPGAs )

Synthesis is based on Yosys. You need to select your board in common.mk which is the name of a directory inside inside system/fpga_config/ which has configuration files specific to that board. You should also check inside your board directory for config.mk for further board-specific configuration options. Then you can run make upload in the top level directory and it should create the bitstream and upload it.

This list shows the software needed and the versions used during development

• yosys : 0.35
• bin86 : 0.16.21
• GNU Make : 4.4.1
• xxd : 2022-01-14
• POSIX coreutils : GNU coreutils 9.4

Additionally, for ECP5 FPGAs:

• prjtrellis : 1.4 ( database commit 4dda149b9e4f1753ebc8b011ece2fe794be1281a )
• nextpnr : 0.6

Additionally, for FPGAs using the foboot bootloader

• dfu-util : 0.11

License and Copyright

All parts of this project and files in this repository are licensed under the GNU General Public License version 3 or later

Efthymios Kritikos is the copyright owner for all files except the following:

File	Copyright owner	Original license
system/fpga_config/OrangeCrab_r0.2.1/pin_constraint.pcf	Greg Davill	MIT

Version names

The version name consist of three numbers:

1. The CPU that this version aims to be compatible with
2. The specific milestone
3. Patch level

For example v1.3.2 aims to support 80186 code, is on the fourth milestone and has 2 bug fixes since the milestone was reached. A "-dev" suffix denotes that the code is in the process to become that version, so in-between that and the previous.